Provided is a semiconductor device and a method for forming the same. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.
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1. A semiconductor device comprising: a substrate having one surface and another surface opposite the one surface; a first semiconductor region of a first conductivity type and formed in the substrate; a second semiconductor region of a second conductivity type, the second semiconductor region being selectively provided in a first surface layer, that includes the one surface, of the substrate; a first electrode in contact with the second semiconductor region to form a junction between the second semiconductor region and the first electrode; a third semiconductor region of the first conductivity type and provided in a second surface layer, that includes the another surface, of the substrate, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region; a fourth semiconductor region of the second conductivity type and provided in the substrate at a location deeper than the third semiconductor region from the another surface; and a second electrode in contact with the third semiconductor region, an end portion of the fourth semiconductor region being located at a position that is at least a diffusion length of a minority carrier toward an inside from an end portion of the junction between the second semiconductor region and the first electrode.
The semiconductor device consists of a substrate with top and bottom surfaces. Inside the substrate is a first semiconductor region of a first conductivity type (e.g., N-type). A second semiconductor region, with opposite conductivity (e.g., P-type), is located in the top surface layer. A first electrode makes contact with this second region, forming a junction. On the bottom surface layer is a third semiconductor region (first conductivity type) with a higher impurity concentration than the first region. A fourth semiconductor region (second conductivity type) is located deeper in the substrate than the third region. A second electrode contacts the third region. Crucially, the fourth region extends at least a minority carrier diffusion length inward from the junction between the first electrode and second semiconductor region.
2. The semiconductor device according to claim 1 , further comprising: a fifth semiconductor region of the first conductivity type and provided in the substrate so as to extend from the another surface to a position deeper from the another surface than that of the third semiconductor region, the fifth semiconductor region having an impurity concentration that is higher than the impurity concentration of the first semiconductor region and is lower than the impurity concentration of the third semiconductor region, wherein an end portion of the third semiconductor region is located further inward than a side surface of the first semiconductor region, and the fifth semiconductor region and the second electrode contact each other at a position further outward than a position of the third semiconductor region.
The semiconductor device described in claim 1 also has a fifth semiconductor region (first conductivity type) extending from the bottom surface deeper than the third region. This fifth region has an impurity concentration higher than the first region but lower than the third. The third region's edge is located inward from the side of the first region. The fifth region and the second electrode make contact with each other further outward than the third region. This adds a deeper, moderately doped region connecting to the bottom electrode.
3. The semiconductor device according to claim 2 , further comprising a sixth semiconductor region of the second conductivity type, the sixth semiconductor region being provided in the fifth semiconductor region to be further outward than the third semiconductor region so as to be separated from the third semiconductor region and the fourth semiconductor region.
The semiconductor device described in claim 2 further includes a sixth semiconductor region with the second conductivity type. This sixth region is positioned within the fifth region but is located outward from the third and fourth regions, maintaining a separation between them. This creates a localized P-type region within the deeper N-type (fifth) region.
4. The semiconductor device according to claim 2 , wherein the fifth semiconductor region is formed by a plurality of proton irradiation processes to include a plurality of the fifth semiconductor regions, and the plurality of the fifth semiconductor regions are arranged at different depths from the another surface of the first semiconductor region.
In the semiconductor device described in claim 2, the fifth semiconductor region is created through multiple proton irradiation steps. This results in several distinct fifth semiconductor regions at varying depths from the bottom surface of the first semiconductor region. This allows for precise control of the doping profile.
5. The semiconductor device according to claim 2 , wherein the end portion of the fourth semiconductor region is located further inward than the end portion of the third semiconductor region.
In the semiconductor device described in claim 2, the edge of the fourth semiconductor region is positioned further inward than the edge of the third semiconductor region. This relative positioning of the two doped regions is important for device performance.
6. The semiconductor device according to claim 2 , wherein the contact between the fifth semiconductor region and the second electrode is a Schottky junction.
In the semiconductor device described in claim 2, the connection between the fifth semiconductor region and the second electrode forms a Schottky junction. This type of junction offers different electrical characteristics compared to an ohmic contact.
7. The semiconductor device according to claim 1 , wherein an occupation area ratio of a total surface area of the fourth semiconductor region to a total surface area of an active region in which a main current flows is equal to or greater than 90%, and equal to or less than 98%.
In the semiconductor device described in claim 1, the area occupied by the fourth semiconductor region, relative to the active region where the main current flows, ranges from 90% to 98%. This describes the spatial coverage of this doped region within the device.
8. The semiconductor device according to claim 1 , wherein a contact end portion is defined by a plane that projects through the end portion of the junction and from the one surface to the another surface, wherein a first occupation area ratio is defined as a total surface area of only portions of the fourth semiconductor region that are further inward relative to the contact end portion, to a total surface area of an active region in which a main current flows, wherein a second occupation area ratio is defined as a total surface area of only portions of the fourth semiconductor region that are further outward relative to the contact end portion, to a total surface area of an edge termination structure portion, further wherein the first occupation area ratio is higher than the second occupation area ratio.
In the semiconductor device described in claim 1, a vertical plane is defined that extends from the top surface, through the junction, to the bottom surface forming a "contact end portion". The area of the fourth semiconductor region inward of this plane compared to the active region is the "first occupation area ratio." The area of the fourth semiconductor region outward of this plane compared to the edge termination structure is the "second occupation area ratio". The first occupation area ratio is larger than the second.
9. The semiconductor device according to claim 1 , wherein a contact end portion is defined by a plane that projects through the end portion of the junction and from the one surface to the another surface, wherein a length of the fourth semiconductor region, which is further inward relative to the contact end portion, measured along a direction parallel to the another surface is equal to or greater than 250 μm.
In the semiconductor device described in claim 1, a vertical plane is defined that extends from the top surface, through the junction, to the bottom surface forming a "contact end portion". The length of the fourth semiconductor region located inward of this plane, measured parallel to the bottom surface, is at least 250 μm.
10. The semiconductor device according to claim 1 , wherein a contact end portion is defined by a plane that projects through the end portion of the junction and from the one surface to the another surface, wherein the fourth semiconductor region is located further inward relative to the contact end portion, and a distance of a separation portion between the contact end portion and the end portion of the fourth semiconductor region has a length equal to or less than 2000 μm.
In the semiconductor device described in claim 1, a vertical plane is defined that extends from the top surface, through the junction, to the bottom surface forming a "contact end portion". The fourth semiconductor region is inward relative to this plane. The separation distance between this plane and the edge of the fourth semiconductor region is 2000 μm or less.
11. The semiconductor device according to claim 1 , further comprising a fifth semiconductor region of the first conductivity type provided in the substrate at a position deeper than the fourth semiconductor region from the another surface so as to be separated from the fourth semiconductor region, the fifth semiconductor region having an impurity concentration that is higher than the impurity concentration of the first semiconductor region and that is lower than the impurity concentration of the third semiconductor region.
The semiconductor device described in claim 1 also contains a fifth semiconductor region of the first conductivity type located deeper than the fourth semiconductor region. This region is isolated from the fourth region and its impurity concentration is higher than the first region but lower than the third.
12. The semiconductor device according to claim 1 , wherein the fourth semiconductor region has a planar shape in which at least two sides are parallel to two sides of the first semiconductor region having a rectangular shape in a plan view, the two sides of the first semiconductor region sharing a vertex, and a connection portion between the two sides of the fourth semiconductor region is located further inward than an intersection point of the two sides of the first semiconductor region.
In the semiconductor device described in claim 1, the fourth semiconductor region has a planar shape with at least two sides parallel to two sides of the rectangular first semiconductor region. These two sides of the first semiconductor region share a vertex. The connection point between the two sides of the fourth region is located further inward than the vertex of the first region.
13. The semiconductor device according to claim 1 , further comprising: an active region in which a main current flows; and a termination structure portion which surrounds the active region and holds a breakdown voltage, wherein the fourth semiconductor region is provided in the active region, and an avalanche breakdown voltage of the active region is less than an avalanche breakdown voltage of the termination structure portion.
The semiconductor device described in claim 1 includes an active region where most current flows and a surrounding termination structure that prevents voltage breakdown. The fourth semiconductor region is located in the active region, and the breakdown voltage of the active region is less than the breakdown voltage of the termination structure.
14. The semiconductor device according to claim 1 , wherein all of the fourth semiconductor region is disposed directly underneath the first electrode.
In the semiconductor device described in claim 1, the entire fourth semiconductor region is positioned directly underneath the first electrode. This defines a specific spatial relationship between these components.
15. The semiconductor device according to claim 1 , wherein the fourth semiconductor region is disposed directly underneath a center of the first electrode.
In the semiconductor device described in claim 1, the fourth semiconductor region is positioned directly under the center of the first electrode. This specifies a centered alignment of these two components.
16. The semiconductor device according to claim 1 , wherein the fourth semiconductor region is disposed directly above the third semiconductor region.
In the semiconductor device described in claim 1, the fourth semiconductor region is positioned directly above the third semiconductor region. This describes a vertical stacking of these doped regions.
18. A semiconductor device comprising: a substrate having one surface and another surface opposite the one surface; a first semiconductor region of a first conductivity type and formed in the substrate; a second semiconductor region of a second conductivity type, the second semiconductor region being selectively provided in a first surface layer, that includes the one surface, of the substrate; a first electrode in contact with the second semiconductor region to form a junction between the second semiconductor region and the first electrode; a third semiconductor region of the first conductivity type and provided in a second surface layer, that includes the another surface, of the substrate, the third semiconductor region having a higher impurity concentration than that of the first semiconductor region; a fourth semiconductor region of the second conductivity type and provided in the substrate at a location deeper than the third semiconductor region from the another surface; a field limiting ring disposed in the first surface layer, an end portion of said junction being located at a position that is toward an inside of the device from the field limiting ring; and a second electrode in contact with the third semiconductor region, an end portion of the fourth semiconductor region being located at a position that is toward said inside from said end portion of said junction.
The semiconductor device consists of a substrate with top and bottom surfaces. A first semiconductor region of a first conductivity type is within the substrate. A second semiconductor region, with opposite conductivity, is in the top surface layer. A first electrode contacts this second region, forming a junction. On the bottom surface layer is a third semiconductor region (first conductivity type) with a higher impurity concentration than the first region. A fourth semiconductor region (second conductivity type) is deeper than the third region. A field limiting ring is located in the top surface layer, with the junction's edge positioned inside of the ring. A second electrode contacts the third region, and the fourth region's edge is inside the junction's edge.
19. The semiconductor device according to claim 18 , wherein all of the fourth semiconductor region is disposed directly underneath the first electrode.
In the semiconductor device described in claim 18, the entire fourth semiconductor region is positioned directly underneath the first electrode. This defines a specific spatial relationship between these components.
20. The semiconductor device according to claim 18 , wherein the fourth semiconductor region is disposed directly underneath a center of the first electrode.
In the semiconductor device described in claim 18, the fourth semiconductor region is positioned directly under the center of the first electrode. This specifies a centered alignment of these two components.
21. The semiconductor device according to claim 18 , wherein the fourth semiconductor region is disposed directly above the third semiconductor region.
In the semiconductor device described in claim 18, the fourth semiconductor region is positioned directly above the third semiconductor region. This describes a vertical stacking of these doped regions.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 7, 2015
September 26, 2017
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