A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
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1. A multi-layer semiconductor device, comprising: at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including: a first section having first and second opposing surfaces and a plurality of electrical connections extending between select portions of the first and second surfaces, wherein the first surface of the first section corresponds to the first surface of the at least two semiconductor structures; a second section having first and second opposing surfaces, wherein the first surface of the second section is disposed over and coupled to the second surface of the first section, the second section including: a device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces, wherein the second surface of the device layer corresponds to the second surface of the second section; and an insulating layer having first and second opposing surfaces, wherein the first surface of the insulating layer corresponds to the first surface of the second section; one or more conductive structures extending between select ones of the plurality of electrical connections in the first section, select ones of the plurality of electrical connections in the device layer of the second section, and select portions on or beneath the second surface of each of the at least two semiconductor structures; and one or more interconnect pads having first and second opposing surfaces and one or more sides, wherein the first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of each of the at least two semiconductor structures and select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures; the multi-layer semiconductor device further comprising: a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures, the via joining layer having first and second opposing surfaces and at least one conductive structure extending between select portions of the first and second surfaces, wherein the at least one conductive structure is electrically coupled to second surfaces of select ones of the one or more interconnect pads on the at least two semiconductor structures to form one or more electrical connections between the at least two semiconductor structures.
A multi-layer semiconductor device stacks at least two semiconductor structures. Each structure has top and bottom surfaces and contains a first section (with electrical connections between its top and bottom) and a second section. The second section comprises a device layer (also with electrical connections) and an insulating layer. Conductive structures connect electrical connections in the first section, the device layer, and areas on or below the bottom surface of the structure. Interconnect pads are placed on or below the bottom surfaces of the structures and are electrically linked to the conductive structures. A via joining layer, with at least one conductive structure, sits between and connects the bottom surfaces of the structures, forming electrical connections between them via the interconnect pads.
2. The multi-layer semiconductor device of claim 1 wherein at least one of the one or more electrical connections formed between the at least two semiconductor structures is an electrical connection between select ones of the plurality of electrical connections in the first section of a first one of the at least two semiconductor structures and select ones of the plurality of electrical connections in the first section of a second one of the at least two semiconductor structures.
In the multi-layer semiconductor device, as described previously, at least one electrical connection between the stacked semiconductor structures is made by connecting electrical connections within the first section of one semiconductor structure to electrical connections within the first section of another semiconductor structure. Essentially, electrical signals are passed directly between the first sections of the stacked structures.
3. The multi-layer semiconductor device of claim 1 wherein a predetermined distance of between about one micrometer (μm) and about four μm exists between the first and second surfaces of the via joining layer, wherein the predetermined distance corresponds to a height of the via joining layer and a height of the at least one conductive structure.
In the multi-layer semiconductor device, as described previously, the via joining layer, which connects the bottom surfaces of the semiconductor structures, has a thickness (height) between 1 and 4 micrometers. This predetermined distance includes the height of the via joining layer itself and the height of any conductive structures it contains.
4. The multi-layer semiconductor device of claim 1 wherein a predetermined distance of between about six micrometers (μm) and about ten μm exists between the first and second surfaces of the second section in a first one of the at least two semiconductor structures, wherein the predetermined distance corresponds to a height of the second section.
In the multi-layer semiconductor device, as described previously, the second section of at least one of the semiconductor structures has a thickness (height) between 6 and 10 micrometers. This predetermined distance corresponds to the overall height of the second section.
5. The multi-layer semiconductor device of claim 1 wherein the at least one conductive structure in the via joining layer includes a plurality of conducting metals, the plurality of metals including at least one of Nickel (Ni), Copper (Cu), Aluminum (Al), Zinc (Zn) and Tin (Sn).
The invention relates to multi-layer semiconductor devices, specifically addressing the challenge of improving electrical conductivity and reliability in via joining layers that connect different semiconductor layers. The device includes a via joining layer with at least one conductive structure composed of multiple conducting metals. These metals are selected from a group including Nickel (Ni), Copper (Cu), Aluminum (Al), Zinc (Zn), and Tin (Sn). The use of multiple metals in the conductive structure enhances electrical performance, reduces resistance, and improves durability by mitigating issues like oxidation and electromigration. The via joining layer facilitates electrical connections between semiconductor layers, ensuring efficient signal transmission and structural integrity. The selection of metals allows for customization based on specific conductivity, thermal stability, and cost requirements. This design is particularly useful in advanced semiconductor packaging and integrated circuit manufacturing, where reliable interlayer connections are critical for device performance and longevity. The invention focuses on optimizing the conductive properties of the via joining layer to support high-performance semiconductor applications.
6. The multi-layer semiconductor device of claim 1 wherein the via joining layer comprises an oxide material.
In the multi-layer semiconductor device, as described previously, the via joining layer, which connects the bottom surfaces of the semiconductor structures, is made of an oxide material.
7. The multi-layer semiconductor device of claim 1 wherein the second section of a first one of the at least two semiconductor structures includes a first conductive structure of the one or more conductive structures, the first conductive structure having first and second opposing surfaces extending between the first and second surfaces of the second section of the first one of the at least two semiconductor structures, wherein the first surface of the first conductive structure has first dimensions and the second surface of the first conductive structure has second, different dimensions.
In the multi-layer semiconductor device, as described previously, the second section of at least one semiconductor structure contains a conductive structure that extends between the top and bottom surfaces of the second section. The top and bottom surfaces of this conductive structure have different dimensions, i.e., the shape or area of the top is different from the bottom.
8. The multi-layer semiconductor device of claim 7 wherein the first surface of the first conductive structure has a diameter between about two μm and about three μm.
In the multi-layer semiconductor device as described with a conductive structure having different dimensions, the top surface of that conductive structure has a diameter between 2 and 3 micrometers.
9. The multi-layer semiconductor device of claim 7 wherein the second surface of the first conductive structure has a diameter between about two μm and about three μm.
In the multi-layer semiconductor device as described with a conductive structure having different dimensions, the bottom surface of that conductive structure has a diameter between 2 and 3 micrometers.
10. The multi-layer semiconductor device of claim 1 wherein at least one of the one or more conductive structures extending between select ones of the plurality of electrical connections in the first section and select ones of the plurality of electrical connections in the device layer of the second section is provided as a through insulator via (TIV) conductive structure.
In the multi-layer semiconductor device, as described previously, at least one of the conductive structures that connect the electrical connections in the first section to those in the device layer of the second section is implemented as a Through Insulator Via (TIV). This means the connection is made through the insulating material.
11. The multi-layer semiconductor device of claim 1 wherein the insulating layer of the second section is provided from an oxide material including at least one of silicon dioxide (SiO 2 ) and chemically treated silicon oxide (SiO), wherein the SiO is chemically treated through a chemical vapor deposition process.
In the multi-layer semiconductor device, as described previously, the insulating layer within the second section is made from an oxide material. This oxide material is either silicon dioxide (SiO2) or chemically treated silicon oxide (SiO), where the SiO is treated using a chemical vapor deposition (CVD) process.
12. The multi-layer semiconductor device of claim 11 wherein at least one of the one or more conductive structures extending between select ones of the plurality of electrical connections in the first section and select ones of the plurality of electrical connections in the device layer of the second section is provided as a through oxide via (TOV) conductive structure.
In the multi-layer semiconductor device with the insulating layer of the second section as silicon dioxide (SiO2) or chemically treated silicon oxide (SiO), at least one of the conductive structures connecting the electrical connections in the first section to those in the device layer of the second section is a Through Oxide Via (TOV).
13. The multi-layer semiconductor device of claim 1 wherein the device layer of the second section further comprises: one or more circuit components disposed between the first and second surfaces of the device layer, wherein the one or more circuit components are electrically coupled to select ones of the plurality of electrical connections.
In the multi-layer semiconductor device, as described previously, the device layer within the second section contains one or more circuit components located between its top and bottom surfaces. These circuit components are electrically connected to some of the electrical connections within the device layer.
14. The multi-layer semiconductor device of claim 1 wherein the device layer of the second section includes an oxide material which is deposited over the second surface of the insulating layer.
In the multi-layer semiconductor device, as described previously, the device layer of the second section includes an oxide material deposited on top of the insulating layer.
15. The multi-layer semiconductor device of claim 1 wherein at least the second section is fabricated using Silicon-On-Insulator (SOI) fabrication techniques.
In the multi-layer semiconductor device, as described previously, at least the second section of the semiconductor structures is manufactured using Silicon-On-Insulator (SOI) fabrication techniques.
16. The multi-layer semiconductor device of claim 1 wherein the first section is fabricated using either SOI or bulk complementary metal-oxide semiconductor (CMOS) fabrication techniques.
In the multi-layer semiconductor device, as described previously, the first section of the semiconductor structures is manufactured using either Silicon-On-Insulator (SOI) or bulk Complementary Metal-Oxide Semiconductor (CMOS) fabrication techniques.
17. The multi-layer semiconductor device of claim 1 wherein the first section and the second section are substantially the same.
In the multi-layer semiconductor device, as described previously, the first section and the second section of the semiconductor structures are substantially the same.
18. The multi-layer semiconductor device of claim 1 wherein a first one of the at least two semiconductor structures is provided having a first form factor and a second one of the at least two semiconductor structures is provided having a second different, form factor.
In the multi-layer semiconductor device, as described previously, the different semiconductor structures have different shapes or sizes (form factors). One structure has a first form factor, while another has a different form factor.
19. The multi-layer semiconductor device of claim 1 wherein the multi-layer semiconductor device is integrated into a communications device.
The multi-layer semiconductor device, as described previously, is incorporated into a communications device.
20. The multi-layer semiconductor device of claim 1 wherein at least one of the at least two semiconductor structures further includes: a third section having first and second opposing surfaces, wherein the first surface of the third section is disposed over and coupled to the second surface of the second section, the third section including: a device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces, wherein the second surface of the device layer corresponds to the second surface of the third section; and an insulating layer having first and second opposing surfaces, wherein the first surface of the insulating layer corresponds to the first surface of the third section, wherein at least one of the one or more conductive structures in the at least one of the at least two semiconductor structures extends between select ones of the plurality of electrical connections in the device layer of the second section, select ones of the plurality of electrical connections in the device layer of the third section, and select portions on or beneath the second surface of the at least one of the at least two semiconductor structures.
In the multi-layer semiconductor device, as described previously, at least one of the semiconductor structures contains a third section. This third section is similar to the second section, having a device layer and an insulating layer. At least one conductive structure extends between electrical connections in the device layer of the second section, electrical connections in the device layer of the third section, and portions on or beneath the bottom surface of the semiconductor structure. Essentially, adding another stacked layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 11, 2015
October 3, 2017
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