Semiconductor package

1. A semiconductor package comprising: a substrate having at least one groove formed in a solder resist layer on a top surface of the substrate to expose an underlying printed circuit board; and a semiconductor device mounted on the substrate, wherein the at least one groove includes long and short sides and has a shape including a first region and second region that are connected to each other, wherein the first region is covered by the semiconductor device and the second region is uncovered by the semiconductor device, wherein one of the short sides is included in the first region and one of the short sides is included in the second region and an underfill material fills the groove.

2. The semiconductor package of claim 1 , further comprising: an underfill material layer filling the first region and the second region and formed between the substrate and the semiconductor device.

3. The semiconductor package of claim 2 , wherein the underfill material layer is fully filled between the substrate and the semiconductor device.

4. The semiconductor package of claim 2 , wherein the underfill material layer comprises: a plurality of underfill members spaced apart from each other, wherein a plurality of grooves are respectively filled by the plurality of underfill members.

5. The semiconductor package of claim 1 , wherein the at least one groove comprises two first sides divided into the first region and the second region and two second sides, each included in one of the first region and the second region, wherein the first sides are longer than the second sides.

6. The semiconductor package of claim 5 , wherein one of the two second sides is in the second region and the other one is in the first region.

7. The semiconductor package of claim 5 , wherein the two second sides are parallel to each other in the second region.

8. The semiconductor package of claim 5 , wherein the second sides are equal to or less than one half a length of the first sides.

9. The semiconductor package of claim 5 , wherein the two first sides are not parallel to each other.

10. The semiconductor package of claim 5 , wherein a space between the two first sides tapers from the second region to the first region.

11. The semiconductor package of claim 1 , wherein lower or side surfaces of the groove are inclined.

12. The semiconductor package of claim 11 , wherein the lower surfaces of the groove are deeper in the second region than in the first region.

13. The semiconductor package of claim 1 , wherein the substrate comprises a wiring layer and a solder resist layer, wherein the groove are formed by etching a part of the solder resist layer.

14. A semiconductor package comprising: a substrate having at least one groove in an upper surface, the groove including long sides and short sides; a semiconductor device mounted on the substrate and exposing a portion of the groove and covering the remaining portion of the groove, with one short side of the groove covered by the semiconductor device and another short side of the groove exposed; and an underfill material layer filling the exposed portion and the remaining portion of the groove and formed between the substrate and the semiconductor device.

15. The semiconductor package of claim 14 , wherein a part of the underfill material layer that fills the exposed portion and the remaining portion of the groove and another part formed between the substrate and the semiconductor device are integrally formed with each other.

16. A semiconductor package, comprising: a substrate including a printed circuit board and a solder resist layer coated on a top surface thereof; a groove including two short sides and two longs sides formed in the solder resist layer to enhance flow of underfill material with which the groove is filled under a semiconductor device; and a semiconductor device mounted on the top surface of the substrate, leaving a portion of the groove exposed.

17. The semiconductor package of claim 16 , further comprising an underfill material between the semiconductor device and substrate and at least partially filling the groove.

18. The semiconductor package of claim 17 , wherein the semiconductor device includes a second semiconductor package.

19. The semiconductor package of claim 17 wherein the underfill material is in areas between the semiconductor device and the substrate in addition to that in the groove.

20. The semiconductor package of claim 17 , wherein the groove is narrower under the semiconductor device than outside a boundary of the semiconductor device.