A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
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1. A high voltage semiconductor transistor, comprising: a semiconductor substrate having an implanted oxygen layer; a first well region; an insulating structure; a gate structure near the insulating structure over the first well region; a drain region in the first well region across the insulating structure from the gate structure, wherein the drain region comprises a first drain portion and a second drain portion; a source region disposed on a side of the gate structure opposite from the drain region; and an isolation feature in the first well region, the isolation feature at least partially surrounding the insulating structure, the gate structure, the source region, and the first drain portion, wherein a portion of the isolation feature is closer to the drain region than the source region, wherein the first drain portion is separated from the second drain portion by the isolation feature and, wherein the isolation feature is proximate to the implanted oxygen layer.
A high-voltage semiconductor transistor (IGBT) includes a semiconductor substrate with an implanted oxygen layer to reduce leakage. A first well region is formed in the substrate. An insulating structure and a gate structure are placed near the insulating structure over the first well. A drain region (split into two portions) and a source region are formed in the first well on opposite sides of the gate. A deep trench isolation feature surrounds the insulating structure, gate, source, and one portion of the drain, physically separating the two drain portions. This isolation feature is positioned near the implanted oxygen layer.
2. The transistor of claim 1 , wherein the semiconductor substrate is lightly doped having a first type of conductivity, wherein a portion of the lightly doped semiconductor substrate includes the implanted oxygen layer below a top surface of the lightly doped semiconductor substrate.
The high-voltage semiconductor transistor described previously utilizes a lightly doped semiconductor substrate with an implanted oxygen layer positioned beneath the surface to minimize substrate leakage. Specifically, the implanted oxygen layer is within a portion of the lightly doped semiconductor substrate and below the top surface.
3. The transistor of claim 2 , wherein the first well region has a second type of conductivity and is formed over the lightly doped semiconductor substrate.
The transistor described previously uses a first well region with a conductivity type (e.g., p-type) opposite to that of the lightly doped semiconductor substrate (e.g., n-type). The first well region is formed on top of the lightly doped semiconductor substrate.
4. The transistor of claim 3 , further comprising: a second well region in the first well region and having the first type of conductivity.
The transistor described previously also incorporates a second well region within the first well region. This second well region has the same conductivity type as the lightly doped semiconductor substrate (opposite to the first well region), providing a region for source formation.
5. The transistor of claim 4 , wherein the insulating structure is over and partially embedded in the first well region and not contacting the second well region.
In the transistor described previously, the insulating structure is positioned above and partially embedded within the first well region. Critically, this insulating structure does not make contact with the second well region, preventing unwanted current paths.
6. The transistor of claim 4 , wherein the source region is in the second well region.
In the transistor described previously, the source region is located within the second well region. The second well creates a specific region for the source with controlled doping.
7. The transistor of claim 4 , wherein the isolation feature is a deep trench isolation feature and at least partially surrounds the second well region.
In the transistor described previously, the isolation feature is implemented using a deep trench isolation (DTI) structure. This DTI at least partially surrounds the second well region, further isolating it and other components from leakage paths and improving device performance.
8. The transistor of claim 2 , wherein the implanted oxygen layer has a peak oxygen concentration at about 300 nm from the top surface of the lightly doped semiconductor substrate.
In the transistor described previously, the implanted oxygen layer has a peak concentration of oxygen at a depth of approximately 300 nanometers from the top surface of the lightly doped semiconductor substrate. This specific depth optimizes leakage reduction.
9. The transistor of claim 1 , wherein the implanted oxygen layer includes oxygen concentration above about 5E20 atoms/cm 3 and is about 100 nm thick.
In the transistor described previously, the implanted oxygen layer has a high concentration of oxygen atoms, specifically above 5E20 atoms per cubic centimeter. This layer is approximately 100 nanometers thick to effectively suppress substrate leakage.
10. The transistor of claim 2 , wherein the implanted oxygen layer is at least 100 nm below the top surface of the lightly doped semiconductor substrate.
In the transistor described previously, the implanted oxygen layer is positioned at least 100 nanometers below the top surface of the lightly doped semiconductor substrate to avoid interfering with surface device characteristics while effectively reducing leakage.
11. The transistor of claim 1 , wherein the source region comprising a first region having the first type of conductivity and a second region having the second type of conductivity.
In the transistor described previously, the source region consists of two distinct regions: a first region with the same conductivity type as the lightly doped semiconductor substrate and a second region with the opposite conductivity type. This creates a specific source profile.
12. The transistor of claim 7 , wherein the deep trench isolation feature contacts the implanted oxygen layer where oxygen concentration is greater than about 1E20 atoms/cm 3 .
In the transistor using a deep trench isolation feature, the deep trench isolation makes contact with the implanted oxygen layer. Specifically, it touches areas where the oxygen concentration exceeds 1E20 atoms per cubic centimeter, maximizing the effectiveness of leakage reduction.
13. The transistor of claim 7 , wherein the deep trench isolation feature comprises thermally grown silicon oxide.
In the transistor described previously with a deep trench isolation feature, the deep trench isolation is made of thermally grown silicon oxide, offering a high-quality insulating barrier.
14. The transistor of claim 7 , wherein the deep trench isolation feature is at least 100 nm wide.
In the transistor using a deep trench isolation feature, the deep trench isolation has a width of at least 100 nanometers. This minimum width ensures adequate isolation and prevents current leakage through the trench.
15. The transistor of claim 4 , wherein the second well region comprises a first portion and a second portion, the first portion surrounding the source region and the second portion extending laterally under the gate structure.
In the transistor described previously, the second well region (where the source resides) consists of two portions. The first portion surrounds the source region itself. The second portion extends laterally beneath the gate structure, influencing the device's electrical characteristics.
16. The transistor of claim 1 , wherein the gate structure comprises a gate electrode, the gate electrode comprising Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or a combination thereof.
In the transistor described previously, the gate structure uses a gate electrode made of a metal or metal compound. This material can be Aluminum (Al), Copper (Cu), Tungsten (W), Titanium (Ti), Tantalum (Ta), Titanium Nitride (TiN), Tantalum Nitride (TaN), Nickel Silicide (NiSi), Cobalt Silicide (CoSi), or a combination thereof.
17. The transistor of claim 1 , wherein the gate structure comprises a gate dielectric, the gate dielectric comprising silicon oxide, a high-K dielectric material, or silicon oxynitride.
In the transistor described previously, the gate structure uses a gate dielectric made of an insulating material. This material can be silicon oxide, a high-K dielectric material (for increased capacitance), or silicon oxynitride.
18. The transistor of claim 1 , wherein the gate structure is formed partly on the insulating structure.
In the transistor described previously, the gate structure is partially formed on top of the insulating structure, affecting the device's capacitance and threshold voltage.
19. A high voltage semiconductor transistor, comprising: a semiconductor substrate; a first well region over the semiconductor substrate; a second well region in the first well region; an insulating structure over and partially embedded in the first well region, the insulating structure isolated from contact with the second well region; a gate structure near the insulating structure over the first well region; a drain region in the first well region across the insulating structure from the gate structure, wherein the drain region comprises a first drain portion adjacent to the insulating structure and a second drain portion farther away from the insulating structure; a source region in the second well region disposed on a side of the gate structure opposite the drain region; and a trench isolation feature in the first well region, the trench isolation feature being proximate to an implanted oxygen layer, wherein the first drain portion is separated from the second drain portion by a portion of the trench isolation feature, and wherein the trench isolation feature surrounds one or more of the second well region, the insulating structure, the gate structure, the source region, and the first drain portion.
A high-voltage semiconductor transistor (IGBT) incorporates a semiconductor substrate and a first well region above it. A second well region is located inside the first well. An insulating structure sits above and partially within the first well, isolated from the second well. A gate structure is placed near the insulating structure, over the first well. A drain region (with two portions) is positioned across the insulating structure from the gate. The source is in the second well, on the opposite side of the gate from the drain. A deep trench isolation feature is near an implanted oxygen layer. This trench divides the drain and surrounds the second well, insulating structure, gate, source, and one drain portion.
20. A high voltage semiconductor transistor, comprising: a semiconductor substrate; a first well region over the semiconductor substrate; a second well region in the first well region; an insulating structure over and partially embedded in the first well region, the insulating structure isolated from contact with the second well region; a gate structure partly on the insulating structure over the first well region; a drain region in the first well region across the insulating structure from the gate structure, wherein the drain region comprises a first drain portion adjacent to the insulating structure and a second drain portion farther away from the insulating structure; a source region in the second well region disposed on a side of the gate structure opposite the drain region; and a trench isolation feature in the first well region, the trench isolation feature being proximate to an implanted oxygen layer, wherein the first drain portion is separated from the second drain portion by a portion of the trench isolation feature, and wherein the trench isolation feature and the implanted oxygen layer together surround one or more of the second well region, the insulating structure, the gate structure, the source region, and the first drain portion.
A high-voltage semiconductor transistor (IGBT) uses a semiconductor substrate with a first well region above it and a second well region inside the first well. An insulating structure sits above and partially within the first well, isolated from the second well. A gate structure sits partly on the insulating structure, above the first well. A drain region (with two portions) is across the insulating structure from the gate. A source is in the second well, on the opposite side of the gate from the drain. A deep trench isolation feature is near an implanted oxygen layer. The trench divides the drain and the trench and implanted oxygen layer together surround the second well, insulating structure, gate, source, and one drain portion.
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June 24, 2016
October 17, 2017
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