A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A high voltage semiconductor transistor, comprising: a semiconductor substrate having an implanted oxygen layer; a first well region; an insulating structure; a gate structure near the insulating structure over the first well region; a drain region in the first well region across the insulating structure from the gate structure, wherein the drain region comprises a first drain portion and a second drain portion; a source region disposed on a side of the gate structure opposite from the drain region; and an isolation feature in the first well region, the isolation feature at least partially surrounding the insulating structure, the gate structure, the source region, and the first drain portion, wherein a portion of the isolation feature is closer to the drain region than the source region, wherein the first drain portion is separated from the second drain portion by the isolation feature and, wherein the isolation feature is proximate to the implanted oxygen layer.
2. The transistor of claim 1 , wherein the semiconductor substrate is lightly doped having a first type of conductivity, wherein a portion of the lightly doped semiconductor substrate includes the implanted oxygen layer below a top surface of the lightly doped semiconductor substrate.
3. The transistor of claim 2 , wherein the first well region has a second type of conductivity and is formed over the lightly doped semiconductor substrate.
4. The transistor of claim 3 , further comprising: a second well region in the first well region and having the first type of conductivity.
5. The transistor of claim 4 , wherein the insulating structure is over and partially embedded in the first well region and not contacting the second well region.
6. The transistor of claim 4 , wherein the source region is in the second well region.
7. The transistor of claim 4 , wherein the isolation feature is a deep trench isolation feature and at least partially surrounds the second well region.
8. The transistor of claim 2 , wherein the implanted oxygen layer has a peak oxygen concentration at about 300 nm from the top surface of the lightly doped semiconductor substrate.
9. The transistor of claim 1 , wherein the implanted oxygen layer includes oxygen concentration above about 5E20 atoms/cm 3 and is about 100 nm thick.
10. The transistor of claim 2 , wherein the implanted oxygen layer is at least 100 nm below the top surface of the lightly doped semiconductor substrate.
11. The transistor of claim 1 , wherein the source region comprising a first region having the first type of conductivity and a second region having the second type of conductivity.
12. The transistor of claim 7 , wherein the deep trench isolation feature contacts the implanted oxygen layer where oxygen concentration is greater than about 1E20 atoms/cm 3 .
13. The transistor of claim 7 , wherein the deep trench isolation feature comprises thermally grown silicon oxide.
14. The transistor of claim 7 , wherein the deep trench isolation feature is at least 100 nm wide.
15. The transistor of claim 4 , wherein the second well region comprises a first portion and a second portion, the first portion surrounding the source region and the second portion extending laterally under the gate structure.
16. The transistor of claim 1 , wherein the gate structure comprises a gate electrode, the gate electrode comprising Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, or a combination thereof.
17. The transistor of claim 1 , wherein the gate structure comprises a gate dielectric, the gate dielectric comprising silicon oxide, a high-K dielectric material, or silicon oxynitride.
18. The transistor of claim 1 , wherein the gate structure is formed partly on the insulating structure.
19. A high voltage semiconductor transistor, comprising: a semiconductor substrate; a first well region over the semiconductor substrate; a second well region in the first well region; an insulating structure over and partially embedded in the first well region, the insulating structure isolated from contact with the second well region; a gate structure near the insulating structure over the first well region; a drain region in the first well region across the insulating structure from the gate structure, wherein the drain region comprises a first drain portion adjacent to the insulating structure and a second drain portion farther away from the insulating structure; a source region in the second well region disposed on a side of the gate structure opposite the drain region; and a trench isolation feature in the first well region, the trench isolation feature being proximate to an implanted oxygen layer, wherein the first drain portion is separated from the second drain portion by a portion of the trench isolation feature, and wherein the trench isolation feature surrounds one or more of the second well region, the insulating structure, the gate structure, the source region, and the first drain portion.
20. A high voltage semiconductor transistor, comprising: a semiconductor substrate; a first well region over the semiconductor substrate; a second well region in the first well region; an insulating structure over and partially embedded in the first well region, the insulating structure isolated from contact with the second well region; a gate structure partly on the insulating structure over the first well region; a drain region in the first well region across the insulating structure from the gate structure, wherein the drain region comprises a first drain portion adjacent to the insulating structure and a second drain portion farther away from the insulating structure; a source region in the second well region disposed on a side of the gate structure opposite the drain region; and a trench isolation feature in the first well region, the trench isolation feature being proximate to an implanted oxygen layer, wherein the first drain portion is separated from the second drain portion by a portion of the trench isolation feature, and wherein the trench isolation feature and the implanted oxygen layer together surround one or more of the second well region, the insulating structure, the gate structure, the source region, and the first drain portion.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 24, 2016
October 17, 2017
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