A three-terminal nano-electro-mechanical field-effect transistor (NEMFET) includes a source electrode, a gate electrode, a drain electrode and a nanoelectromechanically suspended channel bridging the source electrode and the drain electrode. The nanoelectromechanically suspended channel includes a moveable nanowire and a dielectric coating on a surface of the nanowire facing the gate electrode. A thickness of a gap between the nanowire and the gate electrode is determined by a thickness of the dielectric coating.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a three-terminal nano-electro-mechanical field-effect transistor (NEMFET) comprising: a support substrate having a planar upper surface; a source electrode disposed on the planar upper surface of the support substrate; a drain electrode disposed on the planar upper surface of the support substrate; a gate electrode disposed on the planar upper surface of the support substrate between the source electrode and the drain electrode; a nanoelectromechanically suspended channel, the nanoelectromechanically suspended channel comprising a moveable nanowire, the moveable nanowire having two opposing ends that are connected and vertically fixed to the source electrode and the drain electrode, and a gap between the nanowire and a top surface of the gate electrode; wherein a portion of the nanowire over the gate electrode is configured to deflect in a direction perpendicular to the planar upper surface of the support substrate, and a dielectric coating is deposited on the top surface of the gate electrode facing the nanowire as a gate oxide.
2. A device comprising: a three-terminal nano-electro-mechanical field-effect transistor (NEMFET) comprising: a source electrode; a gate structure comprising a gate electrode; a drain electrode; and a nanoelectromechanically suspended channel bridging the source electrode and the drain electrode, the nanoelectromechanically suspended channel comprises a moveable nanowire and a dielectric coating on a surface of the nanowire facing the gate electrode, wherein: a thickness of a gap between the nanowire and the gate electrode is determined by a thickness of the dielectric coating, and during operation of the device, the nanowire is configured to change between a first state and a second state in which the dielectric coating of the nanowire is in contact with the gate structure.
3. The device of claim 2 , wherein the dielectric coating is deposited on a top surface of the gate electrode facing the nanowire as a gate oxide.
4. The device of claim 2 , wherein the dielectric coating comprises a HfO 2 film and is configured as a passivation covering for the nanowire.
5. The device of claim 2 , wherein a diameter of the nanowire is on a same order as the gap between the nanowire and the top surface of the gate electrode.
6. The device of claim 5 , wherein the gap is an air gap having a dimension of 5-95 nanometers.
7. The device of claim 2 , wherein the gap is an air gap having a thickness determined by oxide deposition that reduces the air gap and increases a diameter of the nanowire, and by a difference in thickness between the source electrode and the gate electrode.
8. The device of claim 2 , wherein the nanowire comprises a Ge core and a Si shell.
9. The device of claim 2 , wherein the nanowire having the dielectric coating is configured to be electrostatically attracted to contact the gate structure when a sufficient gate voltage is applied to the gate electrode.
10. The device of claim 2 , wherein the NEMFET is configured to not draw current from the gate electrode and there is no electrical contact with the gate structure and the nanowire.
11. The device of claim 2 , wherein a sub-threshold slope for the device is less than 60 mV/ decade.
12. The device of claim 2 , wherein a nominal current is configured to flow between the source electrode and the drain electrode when no gate voltage is applied to the gate electrode.
13. The device of claim 9 , wherein an off-current flows between the source electrode and the drain electrode when the nanowire having the dielectric coating contacts the gate structure, the off-current being at least 50 times less than a current that flows between the source electrode and the drain electrode when no gate voltage is applied to the gate electrode.
14. The device of claim 12 , wherein a difference between a pull-in voltage and a pull-out voltage is less than 2 V, the pull-in voltage being a voltage applied to the gate electrode to cause an off-current to flow through the nanowire, and the pull-out voltage being a voltage applied to the device to cause the nominal current to resume flowing.
15. The device of claim 2 , wherein an operational speed of the device is more than 120 MHz.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 11, 2014
October 17, 2017
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