A power conversion system may include a plurality of power devices and a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic signature signal associated with the plurality of power devices. The power converter may also include circuitry operably coupled to the plurality of power devices and the sensor. The circuitry may send a respective gate signal to each respective power device of the plurality of power devices, such that each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices.
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1. A power conversion system, comprising: a plurality of power devices; a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic (EM) signature signal associated with the plurality of power devices; and circuitry operably coupled to the plurality of power devices and the sensor, wherein the circuitry is configured to send a respective gate signal to each respective power device of the plurality of power devices, and wherein each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices, wherein the circuitry is configured to identify the maximum time delay from the respective time delays of the plurality of power devices.
A power conversion system adjusts timing signals to improve performance of power devices. It includes multiple power devices (e.g. transistors) to convert voltage, and a sensor that measures voltage, current, or electromagnetic signals from those devices. Circuitry controls the power devices by sending each a gate signal, which switches the device on or off. Crucially, each gate signal has a unique delay applied to it. This "compensation delay" is calculated based on each device's individual response time and the *slowest* response time among all devices. The circuitry identifies the slowest device to synchronize the power devices.
2. The power conversion system of claim 1 , wherein the circuitry is configured to determine the respective time delay for each power device of the plurality of power devices based on a first time at which a test gate signal is transmitted to the power device and a second time at which the sensor detects a voltage, current, or EM signature change associated with the power device.
In the power conversion system described, the circuitry determines each power device's response time by sending a test gate signal and monitoring when the sensor detects a corresponding change in voltage, current, or EM signature. The time difference between sending the signal and detecting the change is the device's time delay. This delay is specific to each power device.
3. The power conversion system of claim 1 , wherein each of the plurality of power devices is electrically connected in parallel with each other.
In the power conversion system, the multiple power devices are electrically connected in parallel. This means they share the same input and output voltage, increasing current capacity, where all devices operate simultaneously.
4. The power conversion system of claim 3 , wherein the gate signal is configured to switch the respective one of the plurality of power devices.
In the power conversion system where the power devices are in parallel, the gate signal is designed to switch the connected power device, enabling or disabling its contribution to the overall power conversion.
5. The power conversion system of claim 1 , wherein each of the plurality of power devices is electrically connected in series with each other.
In the power conversion system, the multiple power devices are electrically connected in series. This means they are chained together, where the output of one device is connected to the input of the next device, increasing the overall voltage capacity.
6. The power conversion system of claim 5 , wherein the gate signal is configured to switch the respective one of the plurality of power devices.
In the power conversion system where the power devices are in series, the gate signal is designed to switch the connected power device, enabling or disabling its contribution to the overall power conversion.
7. The power conversion system of claim 1 , wherein the circuitry is configured to generate the plurality of compensation delays based on a difference between the maximum time delay and the plurality of time delays.
In the power conversion system, the circuitry calculates the compensation delays by finding the difference between the *maximum* time delay observed among all devices, and each individual device's time delay. This difference becomes the compensation delay applied to that device's gate signal, synchronizing the device switching.
8. A method, comprising: determining, via circuitry, a plurality of time delays associated with a plurality of power devices configured to convert a first voltage into a second voltage; identifying, via the circuitry, a maximum time delay based on the plurality of time delays; generating, via the circuitry, a plurality of compensation delays for the plurality of power devices based on the maximum time delay and the plurality of time delays; and sending, via the circuitry, a plurality of gate signals to the plurality of power devices, wherein each gate signal of the plurality of gate signals comprises a respective compensation delay of the plurality of compensation delays.
A method for controlling multiple power devices in a power converter involves these steps: First, the circuitry determines the response time of each power device used to convert voltage. Second, the circuitry identifies the *slowest* response time among all power devices. Third, it calculates a "compensation delay" for each power device based on the *slowest* time and individual response times. Finally, the circuitry sends a gate signal to each power device, but includes its calculated compensation delay. This ensures all devices switch at the same effective time.
9. The method of claim 8 , wherein each power device of the plurality of power devices comprises silicon-carbide (SiC) or gallium-nitride semiconductor material.
In the method for controlling power devices, each power device is made of silicon carbide (SiC) or gallium nitride (GaN). These materials are wide-bandgap semiconductors, enabling higher switching speeds, higher voltage operation, and improved efficiency compared to traditional silicon devices.
10. The method of claim 8 , wherein determining the plurality of time delays comprises: sending a test gate signal to a respective one of the plurality of power devices at a first time; receiving a feedback signal from a sensor, wherein the feedback signal indicates that the voltage or current associated with the respective one of the plurality of power devices has changed at a second time; and measuring an amount of time between the first time and the second time.
This invention relates to power device control systems, specifically methods for determining time delays in power device activation. The problem addressed is the need to accurately measure and compensate for propagation delays in power electronics, ensuring synchronized operation of multiple power devices. The invention provides a method to determine these delays by sending a test gate signal to each power device and measuring the time between signal transmission and the resulting voltage or current change detected by a sensor. This measured time represents the propagation delay for each device, enabling precise timing adjustments to synchronize their operation. The method involves sending a test signal to a power device at a first time, receiving a feedback signal from a sensor indicating a voltage or current change at a second time, and calculating the delay as the difference between these times. This approach ensures accurate delay measurement for each device, improving system performance by compensating for variations in response times. The technique is particularly useful in applications requiring tight synchronization, such as power converters, motor drives, and renewable energy systems. By dynamically measuring and adjusting for these delays, the system achieves more efficient and reliable power delivery.
11. The method of claim 8 , comprising waiting for the plurality of power devices to be switched before determining the plurality of time delays when each of the plurality of power devices is electrically connected in parallel with each other.
In the method for controlling power devices where the devices are connected in parallel, the method includes waiting for the power devices to be switched before determining the plurality of time delays, which makes sure all the devices are in the same state.
12. The method of claim 8 , comprising waiting for the plurality of power devices to be switched before determining the plurality of time delays when each of the plurality of power devices is electrically connected in series with each other.
In the method for controlling power devices where the devices are connected in series, the method includes waiting for the power devices to be switched before determining the plurality of time delays, which makes sure all the devices are in the same state.
13. The method of claim 8 , wherein generating the plurality of compensation delays comprises determining the plurality of compensation delays based on a difference between the maximum time delay and each time delay of the plurality of time delays.
In the method for controlling power devices, generating the compensation delays consists of finding the difference between the *maximum* response time and each individual power device's response time. This difference is used as the delay for that device's gate signal.
14. A non-transitory computer-readable medium comprising computer-executable instructions configured to cause circuitry to: determine a plurality of time delays associated with a plurality of power devices configured to convert a first voltage into a second voltage; identify a maximum time delay based on the plurality of time delays; generate a plurality of compensation delays for the plurality of power devices based on the maximum time delay and the plurality of time delays; and send a plurality of gate signals to the plurality of power devices, wherein each gate signal of the plurality of gate signals comprises a respective compensation delay of the plurality of compensation delays.
A non-transitory computer-readable medium stores instructions for a power converter. The instructions cause the circuitry to: determine the response time for each power device; identify the *slowest* response time among all devices; calculate a "compensation delay" for each device based on the *slowest* time and individual response times; and send each device a gate signal with its calculated compensation delay. This synchronizes the devices to improve voltage conversion.
15. The non-transitory computer-readable of claim 14 , wherein each power device of the plurality of power devices comprises silicon-carbide (SiC) or gallium-nitride semiconductor material.
In the computer-readable medium for power conversion, each power device is made of silicon carbide (SiC) or gallium nitride (GaN). These materials enable higher switching speeds and efficiencies compared to traditional silicon.
16. The non-transitory computer-readable of claim 14 , wherein the computer-readable instructions configured to cause the circuitry to determine the plurality of time delays is further configured to cause the circuitry to: send a gate signal to a respective one of the plurality of power devices at a first time; receive a feedback signal from a sensor, wherein the feedback signal indicates that the voltage or current associated with the respective one of the plurality of power devices has changed at a second time; and measure an amount of time between the first time and the second time.
In the computer-readable medium for power conversion, determining each device's response time involves sending a test gate signal to a device, detecting the resulting change in voltage or current with a sensor, and measuring the time difference between the signal and the change.
17. The non-transitory computer-readable of claim 14 , wherein each of the plurality of power devices is electrically connected in parallel with each other, and wherein the computer-readable instructions are configured to cause the circuitry to wait for the plurality of power devices to be switched before determining the plurality of time delays.
In the computer-readable medium for power conversion where the devices are connected in parallel, the instructions cause the circuitry to wait for the power devices to be switched before determining the plurality of time delays, which makes sure all the devices are in the same state.
18. The non-transitory computer-readable of claim 14 , wherein when each of the plurality of power devices is electrically connected in series with each other, and wherein the computer-readable instructions are configured to cause the circuitry to wait for the plurality of power devices to be switched before determining the plurality of time delays.
In the computer-readable medium for power conversion where the devices are connected in series, the instructions cause the circuitry to wait for the power devices to be switched before determining the plurality of time delays, which makes sure all the devices are in the same state.
19. The non-transitory computer-readable of claim 14 , wherein the computer-readable instructions are configured to cause the circuitry to generate the plurality of compensation delays by determining on a difference between the maximum time delay and each time delay of the plurality of time delays.
In the computer-readable medium for power conversion, generating the compensation delays involves finding the difference between the *maximum* device response time and each individual device's response time, using this difference as the gate signal delay.
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December 29, 2015
October 24, 2017
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