A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor wafer, the method comprising: preparing a semiconductor wafer, the semiconductor wafer including first and second surfaces opposite each other and a notch on an outer periphery of the semiconductor wafer, the notch including a recess on the outer periphery toward a center portion of the semiconductor wafer; forming, by processing the outer periphery of the semiconductor wafer, a first bevel region, the first bevel region including a first slope connecting the first and second surfaces, the first slope having a first height with respect to a straight line extending from a first point to a second point, the first point being a point where the first surface and the first slope meet, and the second point being a point where the second surface and the first slope meet; and forming, by processing the notch, a second bevel region, the second bevel region contacting the recess, the second bevel region including a second slope connecting the first and second surfaces such that the second bevel region is within the notch and the first bevel region is along a rest of the outer periphery of the semiconductor wafer abutting the second bevel region, the second slope having a second height, different from the first height, with respect to a straight line extending from a third point to a fourth point, the third point being a point where the first surface and the second slope meet, and the fourth point being a point where the second surface and the second slope meet.
2. The method of claim 1 , wherein the second height is less than the first height.
3. The method of claim 1 , wherein a thickness of a main body of the semiconductor wafer is at least three times larger than the second height.
4. The method of claim 1 , wherein a depth of the recess is about 0.4 micro meters to about 1.0 micro meters.
5. The method of claim 1 , wherein the forming of the second bevel region comprises: first grinding the notch using a notch wheel having a polishing surface of a first mesh; and second grinding the notch using a notch wheel having a polishing surface of a second mesh, the second mesh being larger than the first mesh.
6. The method of claim 5 , wherein the second mesh includes about 2000 meshes to about 10000 meshes.
7. The method of claim 1 , further comprising: inspecting the semiconductor wafer for defects by performing a heat treatment on the semiconductor wafer after the forming of the second bevel region, the inspecting including, performing the heat treatment on the semiconductor wafer at a first temperature; and performing the heat treatment on the semiconductor wafer at a second temperature, the second temperature being greater than the first temperature.
8. The method of claim 7 , wherein the first temperature is between 1,000 C and 1,150 C.
9. The method of claim 7 , wherein the inspecting further comprises: forming an epitaxial layer on the semiconductor wafer before the performing of the heat treatment on the semiconductor wafer at the first temperature.
10. A semiconductor wafer comprising: a main body including first and second surfaces opposite each other; a notch on an outer periphery of the semiconductor wafer, the notch including a recess on the outer periphery toward a center portion of the semiconductor wafer; a first bevel region along the outer periphery of the main body, the first bevel region including a first slope connecting the first and second surfaces, the first slope having a first height with respect to a straight line extending from a first point to a second point, the first point being a point where the first surface and the first slope meet, and the second point being a point where the second surface and the first slope meet; and a second bevel region in contact with the recess, the second bevel region including a second slope connecting the first and second surfaces such that the second bevel region is within the notch and the first bevel region is along a rest of the outer periphery of the semiconductor wafer abutting the second bevel region, the second bevel region having a second height, different from the first height, with respect to a straight line extending from a third point to a fourth point, the third point being a point where the first surface and the second slope meet, the fourth point being a point where the second surface and the second slope meet.
11. The semiconductor wafer of claim 10 , wherein the main body includes a chip forming region and an edge region surrounding the chip forming region, the notch being in the edge region.
12. The semiconductor wafer of claim 10 , wherein the second height is less than the first height.
13. The semiconductor wafer of claim 10 , wherein a thickness of the main body is at least three times the second height.
14. The semiconductor wafer of claim 10 , wherein a depth of the recess is about 0.4 micro meters to about 1.0 micro meters.
15. The semiconductor wafer of claim 10 , wherein an end of the notch has a curved shape in a view perpendicular to the first surface of the main body.
16. A method of manufacturing a semiconductor wafer, the semiconductor wafer including first and second surfaces opposite each other and a notch on an outer periphery of the semiconductor wafer, the method comprising: first processing the outer periphery of the semiconductor wafer to form a first bevel region, the first bevel region being convexly beveled at a first slope between the first and second surfaces, the first bevel region having a first height at a highest point thereof with respect to a start of the first bevel region; and second processing the notch to form a second bevel region, the second bevel region contacting the notch such that the second bevel region is within the notch and the first bevel region is along a rest of the outer periphery of the semiconductor wafer abutting the second bevel region, the second bevel region having a second slope between the first and second surfaces, the second slope having a second height at a deepest point thereof with respect to the outer periphery, the second height being different from the first height.
17. The method of claim 16 , wherein the second processing includes grinding the notch incrementally using different meshes.
18. The method of claim 17 , wherein the second processing comprises: grinding the notch using a polishing surface having a first mesh; and grinding the notch using a polishing surface having a second mesh, the second mesh being larger than the first mesh.
19. The method of claim 16 , further comprising: first heating the semiconductor wafer to a first temperature; second heating the semiconductor wafer to a second temperature, the second temperature being greater than the first temperature; and inspecting the semiconductor wafer for defects after the second heating.
20. The method of claim 19 , further comprising: forming an epitaxial layer on the semiconductor wafer before the first heating.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 17, 2016
October 31, 2017
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