The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.
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1. A method for fabricating a semiconductor device, the method comprising: forming active patterns on a substrate, the active patterns protruding from the substrate; forming an interlayer dielectric layer on the active patterns, the interlayer dielectric layer including a plurality of grooves that expose the active patterns, the plurality of grooves including a first groove having a first width and a second groove having a second width that is greater than the first width; forming a first conductive layer on inner surfaces of the first and second grooves; forming a first sacrificial layer filling the first and second grooves; performing a first etching process to remove the first sacrificial layer and expose a portion of the first conductive layer; and removing the exposed portion of the first conductive layer to form first conductive patterns on top surfaces and sidewalls of the active patterns in the first and second grooves, wherein the plurality of grooves further comprise a third groove having a third width that is substantially equal to the first width of the first groove, wherein the first conductive patterns are formed in the first, second and third grooves, and wherein the method further comprises removing at least one of the first conductive patterns in the first, second and third grooves.
A method for making a semiconductor device involves creating raised "active patterns" on a substrate. An insulating layer (interlayer dielectric) is formed on top, with grooves cut into it to expose the active patterns. These grooves have different widths: some are narrow, others are wider. A conductive layer is deposited inside all grooves. The grooves are then filled with a sacrificial material, which is etched away to partially expose the conductive layer. The exposed parts of the conductive layer are removed, leaving conductive patterns only on the sides and top of the active patterns within each groove. Critically, there are also third grooves similar in width to the narrow ones, and the conductive patterns are formed in *all* groove types. A key step involves removing some of these conductive patterns from certain grooves.
2. The method of claim 1 , wherein each of the first conductive patterns has a “U” shape in a cross-sectional view.
This method for making a semiconductor device, as described in the previous step, results in conductive patterns that look like a "U" shape when viewed in cross-section. This means the conductive material coats the bottom and sidewalls of the groove where it meets the active pattern, forming the U.
3. The method of claim 2 , wherein each of the first conductive patterns has an uppermost top surface that is positioned below a top surface of the interlayer dielectric layer and above a top surface of the active pattern.
In this "U" shaped conductive pattern fabrication method, the top surface of the "U" is lower than the top of the insulating layer that contains the grooves, and higher than the top surface of the active pattern protruding from the substrate in which the groove is cut.
4. The method of claim 3 , wherein the uppermost top surface of the first conductive pattern in the second groove is higher than that of the first conductive pattern in the first groove relative to the substrate.
Continuing with the previous method steps, the top of the "U" shaped conductive pattern in the *wider* groove sits higher than the top of the "U" shaped conductive pattern in the *narrower* groove, relative to the underlying substrate. This height difference is achieved during the fabrication process.
5. The method of claim 1 , wherein the first etching process includes an anisotropic dry etching process using a mixture of hydrogen (H2) and nitrogen (N2) as an etch gas.
The method for making a semiconductor device detailed previously uses a specific etching process to remove sacrificial layer material. This etching involves an anisotropic dry etch (directional etching) using a gas mixture of hydrogen (H2) and nitrogen (N2).
6. The method of claim 1 , wherein removing the at least one of the first conductive patterns in the first, second and third grooves includes removing the first conductive patterns in the first groove and the second groove, wherein removing the first conductive patterns in the first groove and the second groove comprises: forming a second sacrificial layer filling the first, second and third grooves; forming mask patterns on the second sacrificial layer, the first and second grooves opened by the mask patterns; and performing a second etching process using the mask patterns as an etch mask to remove the second sacrificial layer in the first and second grooves.
The method for making a semiconductor device detailed previously specifies removing some of the first conductive patterns in certain grooves. This involves completely removing the conductive patterns from the narrow and wide grooves, but *not* from the third groove (which is the same width as the narrow one). To do this, a second sacrificial layer is deposited to fill all grooves. Then, a mask is created, leaving only the narrow and wide grooves exposed. A second etching process is performed using this mask to remove the second sacrificial layer from those specific grooves, allowing for selective removal of the conductive patterns.
7. The method of claim 6 , wherein the second etching process includes an anisotropic dry etching process using a mixture of hydrogen (H2) and nitrogen (N2) as an etch gas, and wherein a pulsed bias power is employed as a bias power applied to the substrate while the second etching process is performed.
Continuing the previous method, the second etching process that removes the second sacrificial layer in the narrow and wide grooves is an anisotropic dry etching process that uses a mix of hydrogen (H2) and nitrogen (N2) gas. Crucially, a pulsed bias power is applied to the substrate during this etching step, influencing the etching rate and directionality.
8. The method of claim 6 , after removing the first conductive patterns in the first groove and the second groove, further comprising forming a second conductive layer in the first, second and third grooves, the second conductive layer including a material that is different from that of the first conductive layer.
Continuing the previous method, after the first conductive patterns are removed from the narrow and wide grooves, a *second* conductive layer is deposited in *all* grooves (narrow, wide, and third). This second conductive layer is made of a *different* material than the first conductive layer.
9. The method of claim 8 , wherein the first conductive layer includes a metal nitride and the second conductive layer includes aluminum and a metal carbide.
The method for making a semiconductor device detailed previously describes using two different conductive layers. The *first* conductive layer is made of a metal nitride. The *second* conductive layer consists of aluminum and a metal carbide.
10. The method of claim 1 , further comprising: forming first and second sacrificial gate patterns crossing the active patterns on the substrate prior to forming the interlayer dielectric layer, wherein forming the interlayer dielectric layer includes covering sidewalls of each of the first and second sacrificial gate patterns with the interlayer dielectric layer, and removing the first and second sacrificial gate patterns to create spaces that serve as the first and second grooves.
This method begins with forming temporary "sacrificial gate patterns" that cross over the active patterns on the substrate. The insulating layer is then formed, covering the sides of these sacrificial gate patterns. The sacrificial gate patterns are then removed, leaving behind spaces that become the grooves of differing widths mentioned earlier.
11. The method of claim 10 , prior to removing the first and second sacrificial gate patterns, further comprising: forming first source/drain regions on the active patterns at opposing sides of the first sacrificial gate patterns; and forming second source/drain regions on the active patterns at opposing sides of the second sacrificial gate patterns, wherein the first and second source/drain regions have a same conductivity type each other.
Before the sacrificial gate patterns are removed to create the grooves, source/drain regions are created on either side of each gate pattern. The source/drain regions on either side of the *first* sacrificial gate pattern have the same conductivity type. The source/drain regions on either side of the *second* sacrificial gate pattern also have the same conductivity type. This means that these regions are doped in a way that gives them similar electrical properties.
12. The method of claim 1 , wherein forming the first sacrificial layer comprises: forming a first sub-sacrificial layer filling the first and second grooves; recessing the first sub-sacrificial layer; and forming a second sub-sacrificial layer on the recessed first sub-sacrificial layer.
The method describes a process where the sacrificial layer is built in two steps. First, a sub-sacrificial layer is deposited to fill all the grooves. Next, this first sub-sacrificial layer is recessed (etched down), making it shorter. Finally, a second sub-sacrificial layer is deposited on top of the recessed first layer to complete the filling of the groove.
13. A method for fabricating a semiconductor device, the method comprising: forming active patterns on a substrate, the active patterns protruding from the substrate; forming sacrificial gate patterns crossing the active patterns on the substrate; forming an interlayer dielectric layer on sidewalls of the sacrificial gate patterns; removing the sacrificial gate patterns to form a plurality of grooves exposing the active patterns, at least one of the plurality of grooves having a width greater than those of respective others of the plurality of grooves; and forming gate electrodes in the plurality of grooves, wherein forming the gate electrodes includes: forming first work function conductive patterns in the plurality of grooves; removing at least one of the first work function conductive patterns in the plurality of grooves; and forming second work function conductive patterns in the plurality of grooves; wherein each of the first work function conductive patterns has a “U” shape in a cross-sectional view, and wherein each of the first work function conductive patterns has an uppermost top surface positioned below a top surface of the interlayer dielectric layer and higher than a top surface of each of the active patterns.
A method for making a semiconductor device begins by forming raised "active patterns" on a substrate. Then, temporary "sacrificial gate patterns" are created that cross these active patterns. An insulating layer is formed, covering the sides of the sacrificial gates. The sacrificial gate patterns are then removed, leaving grooves behind with differing widths. Gate electrodes are then formed within these grooves. This formation involves depositing a first "work function" conductive pattern, removing some of these patterns selectively, and then depositing a second "work function" conductive pattern. Each first conductive pattern is "U" shaped in cross-section, with the top of the "U" lower than the top of the insulating layer, but higher than the active patterns.
14. The method of claim 13 , wherein forming the first work function conductive patterns comprising: forming a first work function conductive layer in the plurality of grooves; forming a first sacrificial layer in the plurality of grooves; performing a first etching process to expose a portion of the first work function conductive layer in the plurality of grooves; and removing the exposed portion of the first work function conductive layer.
The method for forming semiconductor devices, as described, involves making the first "work function" conductive patterns through a series of steps. First, a conductive layer is deposited to fill all the grooves. Then, a sacrificial layer is deposited on top. This sacrificial layer is partially etched away to expose part of the conductive layer. Finally, the exposed portions of the conductive layer are removed.
15. The method of claim 14 , wherein forming the first sacrificial layer comprises: forming a first sub-sacrificial layer filling the plurality of grooves; recessing the first sub-sacrificial layer; and forming a second sub-sacrificial layer on the recessed first sub-sacrificial layer.
In the previously described method for forming semiconductor devices, the process of creating the first sacrificial layer involves multiple sub-layers. Initially, a first sub-sacrificial layer is deposited to fill the grooves. Subsequently, this layer is etched back or recessed. Finally, a second sub-sacrificial layer is formed on top of the recessed first layer, completing the sacrificial layer structure.
16. The method of claim 14 , wherein removing the at least one of the first work function conductive patterns comprises: forming a second sacrificial layer filling the plurality of grooves in which the first work function conductive patterns are formed; forming a mask pattern on the second sacrificial layer, the mask pattern opening at least one of the plurality of grooves; and performing a second etching process using the mask pattern as an etch mask to remove the second sacrificial layer in the at least one of the plurality of grooves.
In the method for forming semiconductor devices, the process of removing some of the first conductive patterns involves several steps. First, a second sacrificial layer is deposited, filling the grooves where the first conductive patterns exist. A mask pattern is then formed on top of this second sacrificial layer, with openings over the specific grooves where the conductive patterns are to be removed. An etching process uses this mask to selectively remove the second sacrificial layer in those opened grooves.
17. The method of claim 16 , wherein at least one of the first and second etching processes includes an anisotropic dry etching process using a mixture of hydrogen (H2) and nitrogen (N2) as an etch gas.
The method for fabricating a semiconductor device uses anisotropic dry etching with a mixture of hydrogen (H2) and nitrogen (N2) gas for at least one of the etching processes described. This could be either the etching process used to expose portions of the first conductive layer, or the etching process used to remove the second sacrificial layer during selective conductive pattern removal.
18. The method of claim 17 , wherein a first pulsed bias power is employed as a first bias power applied to the substrate while the first etching process is performed; and a second pulsed bias power is employed as a second bias power applied to the substrate while the second etching process is performed.
In the method for forming semiconductor devices where etching processes are utilized, pulsed bias power is employed. During the first etching process (exposing the first work function conductive layer), a *first* pulsed bias power is applied to the substrate. Similarly, during the second etching process (removing the second sacrificial layer), a *second* pulsed bias power is applied. These pulsed bias powers control the ion bombardment energy and directionality during etching.
19. The method of claim 13 , wherein the second work function conductive patterns have an uppermost top surface positioned below the top surface of the interlayer dielectric layer and above uppermost top surfaces of the first work function conductive patterns.
The method, as previously outlined, creates the first and second work function conductive patterns. The top surface of the second work function conductive patterns are lower than the top surface of the surrounding interlayer dielectric layer, but they also sit *above* the uppermost top surfaces of the first work function conductive patterns.
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January 6, 2016
October 31, 2017
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