A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a substrate; a first semiconductor die having a top first die surface and a bottom first die surface, wherein the bottom first die surface is coupled to the substrate, and the first semiconductor die is electrically connected to the substrate; a plurality of adhesive regions spaced apart from each other on the top first die surface; and a second semiconductor die having a top second die surface and a bottom second die surface, wherein the bottom second die surface is adhered to the plurality of adhesive regions, and the second semiconductor die is electrically connected to the substrate, wherein each of the adhesive regions comprises only adhesive material and bridges an entire vertical gap between the top first die surface and the bottom second die surface.
2. The semiconductor device of claim 1 , wherein the substrate is a circuit board.
3. The semiconductor device of claim 1 , wherein the volume directly between the first semiconductor die and the second semiconductor die comprises only the plurality of adhesive regions and air.
4. The semiconductor device of claim 1 , wherein at least a portion of the plurality of adhesive regions are positioned at corners of the first semiconductor die and/or the second semiconductor die.
5. The semiconductor device of claim 1 , wherein at least a portion of the plurality of adhesive regions are positioned along sides of the first semiconductor die and/or the second semiconductor die, at midpoints of the sides.
6. The semiconductor device of claim 1 , wherein at least one of the plurality of adhesive regions is formed at the center of the first semiconductor die and/or the second semiconductor die.
7. The semiconductor device of claim 1 , wherein each of the plurality of adhesive regions has a vertical thickness in a range of 10 μm to 50 μm.
8. The semiconductor device of claim 1 , wherein the adhesive regions are made of at least one of: a plastomer, an elastomer, a thermoplastic elastomer, a thermosetting resin, and a photo-curable resin.
9. The semiconductor device of claim 1 , wherein each of the plurality of adhesive regions comprises: a first adhesive region on and adhered directly to the top first die surface; and a second adhesive region on and adhered directly to the top first die surface and the first adhesive region, and adhered directly to the bottom second die surface.
10. The semiconductor device of claim 9 , wherein the first adhesive region comprises a first adhesive, and the second adhesive region comprises a second adhesive different from the first adhesive.
11. The semiconductor device of claim 10 , wherein the first adhesive has a higher modulus than the second adhesive.
12. The semiconductor device of claim 1 , wherein the second semiconductor die comprises a micro electro-mechanical systems (MEMS) device and the MEMS device comprises a through-hole.
13. The semiconductor device of claim 12 , comprising a cover adhered to the substrate and covering the first semiconductor die, the adhesive regions and the second semiconductor die, wherein the cover comprises a through-hole.
14. The semiconductor device of claim 1 , wherein the first semiconductor die is electrically connected to the substrate by conductive bumps positioned directly between the first semiconductor die and the substrate, and the second semiconductor die is electrically connected to the substrate by conductive wires.
15. A semiconductor device comprising: a substrate; a first semiconductor die having a top first die surface and a bottom first die surface, wherein the bottom first die surface is coupled to the substrate, and the first semiconductor die is electrically connected to the substrate; a plurality of adhesive regions spaced apart from each other on the top first die surface; and a second semiconductor die having a top second die surface and a bottom second die surface, wherein the bottom second die surface is adhered to the plurality of adhesive regions, and the second semiconductor die is electrically connected to the substrate, wherein each of the plurality of adhesive regions comprises: a first adhesive layer on and adhered to the top first die surface; a central layer comprising a central film on top of and adhered to the first adhesive layer; and a second adhesive layer on top of and adhered to the central layer, and adhered to the bottom second die surface.
16. The semiconductor device of claim 15 , wherein the central layer comprises an elastomer.
17. The semiconductor device of claim 15 , wherein the central layer has a lower modulus than the first and second adhesive layers.
18. A semiconductor device comprising: a first semiconductor die having a top first die surface; adhesive material on the top first die surface and comprising a plurality of volumes of the adhesive material separated from each other by a space; and a second semiconductor die having a bottom second die surface, wherein the bottom second die surface is adhered to the plurality of volumes of the adhesive material, wherein the adhesive material comprises the only material that is directly between the first and second semiconductor dies.
19. The semiconductor device of claim 18 , wherein: each of the volumes of the adhesive material comprises a first adhesive volume and a second adhesive volume, both of which are between the first and second semiconductor dies; and each of the volumes of the adhesive material comprises only adhesive material and bridges an entire vertical gap between the top first die surface and the bottom second die surface.
20. The semiconductor device of claim 18 , wherein there is no adhesive material connecting a first volume of the plurality of volumes of the adhesive material to a second volume of the plurality of volumes of the adhesive material.
21. A semiconductor device comprising: a substrate; a first semiconductor die having a top first die surface and a bottom first die surface, wherein the bottom first die surface is coupled to the substrate, and the first semiconductor die is electrically connected to the substrate; a plurality of adhesive regions spaced apart from each other on the top first die surface; and a second semiconductor die having a top second die surface and a bottom second die surface, wherein the bottom second die surface is adhered to the plurality of adhesive regions, and the second semiconductor die is electrically connected to the substrate wherein each of the plurality of adhesive regions comprises: a first adhesive region on and adhered to the top first die surface, the first adhesive region comprising a first adhesive; and a second adhesive region on and adhered to the top first die surface and the first adhesive region, and adhered to the bottom second die surface, the second adhesive region comprising a second adhesive different from the first adhesive.
22. The semiconductor device of claim 21 , wherein the first adhesive has a higher modulus than the second adhesive.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 9, 2016
November 7, 2017
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