A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device comprising: a semiconductor substrate having a chip region, a scribe region located at an outer periphery of said chip region, and a pad region located in said scribe region; a seal ring located between said chip region and said scribe region, the seal ring being apart from the pad region; a wiring layer, formed over said semiconductor substrate, including a first conductive pattern and a plurality of second conductive patterns each disposed within said pad region, said first conductive pattern being disposed along a periphery of said pad region, said second conductive patterns being disposed in an inner area of said pad region with a mutual separation, and said second conductive patterns being electrically isolated from each other; a first insulating film formed over said wiring layer; an uppermost wiring layer, formed over said first insulating film, including a third conductive pattern overlapped with both of said first and second conductive patterns, said third conductive pattern being electrically connected to said first conductive pattern; a second insulating film formed over said uppermost wiring layer, wherein said third conductive pattern is exposed from said second insulating film within said pad region; a third insulating film, formed under said wiring layer; and a lower wiring layer, formed under said third insulating film, including a fourth conductive pattern disposed in said pad region, said second conductive patterns being electrically isolated from said first, third and fourth conductive patterns.
A semiconductor device has a chip area, a surrounding scribe area, and a pad region within the scribe area. A seal ring sits between the chip and scribe areas, separate from the pad region. A wiring layer on the semiconductor substrate contains a first conductive pattern around the pad region's edge and multiple separate second conductive patterns inside the pad region. These second conductive patterns are electrically isolated. A first insulating layer covers this wiring layer. An uppermost wiring layer above includes a third conductive pattern overlapping both the first and second patterns, and connects electrically to the first pattern. A second insulating layer covers the uppermost layer, exposing the third conductive pattern within the pad region. A third insulating film sits under the wiring layer. A lower wiring layer under this film has a fourth conductive pattern in the pad region, electrically isolated from the first, third, and second conductive patterns.
2. The semiconductor device as claimed in claim 1 , wherein said second conductive patterns comprise a plurality of rectangular patterns.
The semiconductor device described in Claim 1, which includes a semiconductor substrate with chip, scribe, and pad regions, wiring layers, and conductive patterns, has second conductive patterns comprised of several rectangular shapes. These rectangular patterns are located inside the pad region, within the scribe region at the edge of the chip.
3. The semiconductor device as claimed in claim 1 , wherein said second conductive patterns are disposed apart inward from an edge of said semiconductor substrate.
In the semiconductor device of Claim 1, which includes a semiconductor substrate with chip, scribe, and pad regions, wiring layers, and conductive patterns, the second conductive patterns are positioned away from the edge of the semiconductor substrate. These electrically isolated patterns sit inside the pad region, within the scribe region at the edge of the chip.
4. The semiconductor device as claimed in claim 3 , wherein said pad region is defined by a first peripheral part opposing said edge of said semiconductor substrate, a second peripheral part reaching said edge and said first peripheral part and a third peripheral part reaching said edge and said first outer peripheral part, said first conductive pattern being disposed along said first, second, and third peripheral parts.
In the semiconductor device of Claim 3 (which includes a semiconductor substrate with chip, scribe, and pad regions, wiring layers, and conductive patterns where the second conductive patterns are positioned away from the substrate edge), the pad region is defined by a first peripheral part opposing the substrate edge, a second and third peripheral part reaching the substrate edge. The first conductive pattern, situated in the wiring layer along the pad region's periphery, runs along these first, second, and third peripheral parts. The second patterns are electrically isolated.
5. The semiconductor device as claimed in claim 1 , wherein said first and second conductive patterns are formed of a copper and said third conductive pattern is formed of aluminum.
In the semiconductor device of Claim 1, which includes a semiconductor substrate with chip, scribe, and pad regions, wiring layers, and conductive patterns, the first and second conductive patterns, situated in the wiring layer along the pad region, are made of copper, while the third conductive pattern, located in the uppermost wiring layer, is made of aluminum.
6. The semiconductor device as claimed in claim 1 , further comprising at least a part of a monitoring device disposed in said scribe region, wherein said monitoring device is electrically connected to said third conductive pattern.
In the semiconductor device of Claim 1, which includes a semiconductor substrate with chip, scribe, and pad regions, wiring layers, and conductive patterns, at least a portion of a monitoring device is present in the scribe region. This monitoring device is electrically connected to the third conductive pattern located in the uppermost wiring layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 1, 2016
November 14, 2017
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