Patentable/Patents/US-9818826
US-9818826

Heterostructure including a composite semiconductor layer

PublishedNovember 14, 2017
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

Patent Claims
20 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. A heterostructure comprising: a composite semiconductor layer including a plurality of sub-layers, wherein the plurality of sub-layers includes: a first sub-layer comprising a plurality of nanowires with a characteristic spacing between each of the nanowires that ranges from 2 nm to 100 nm, a second sub-layer immediately adjacent to the first sub-layer, wherein the second sub-layer includes a partially continuous interior portion with isolated cavities formed therein, the isolated cavities having an arrangement distinct from the spacing between the plurality of nanowires, and wherein the plurality of nanowires of the first sub-layer contact the second sub-layer without penetrating into any of the isolated cavities.

Plain English Translation

A heterostructure used in electronic or optoelectronic devices includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. This structure improves device performance by managing stress and strain in the semiconductor material.

Claim 2

Original Legal Text

2. The heterostructure of claim 1 , wherein the composite semiconductor layer is formed of aluminum nitride.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. In this version, the entire composite semiconductor layer (all the sub-layers) is specifically made from aluminum nitride (AlN), a common semiconductor material.

Claim 3

Original Legal Text

3. The heterostructure of claim 1 , wherein each of the plurality of nanowires has a characteristic diameter in a range of 5-500 nm, and a characteristic length in a range of 50 nm-5 microns.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. Here, the nanowires are specifically sized: their diameter is 5-500 nm and their length is 50 nm - 5 microns.

Claim 4

Original Legal Text

4. The heterostructure of claim 1 , the composite semiconductor layer further comprising a third sub-layer immediately adjacent to the second sub-layer, wherein third sub-layer is essentially continuous.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. This heterostructure has *another* sub-layer immediately next to the porous one which is essentially a continuous, non-porous layer.

Claim 5

Original Legal Text

5. The heterostructure of claim 4 , wherein the third sub-layer is a superlattice including a plurality of alternating tensile and compressive layers.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. This heterostructure has *another* sub-layer immediately next to the porous one which is essentially a continuous, non-porous layer. This continuous sub-layer is a *superlattice* - a stack of alternating layers with tensile and compressive strain.

Claim 6

Original Legal Text

6. The heterostructure of claim 1 , further comprising a substrate, wherein the composite semiconductor layer is immediately adjacent to the substrate.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The entire composite semiconductor layer is grown directly on a substrate material.

Claim 7

Original Legal Text

7. The heterostructure of claim 6 , wherein a top surface of the composite semiconductor layer has a curvature at least five percent less than a top surface of the substrate on which the composite semiconductor layer is located.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The entire composite semiconductor layer is grown directly on a substrate material. The curvature of the top surface of the composite layer is at least 5% flatter than the substrate's top surface, which reduces stress.

Claim 8

Original Legal Text

8. The heterostructure of claim 1 , wherein a characteristic height-to-diameter ratio of each of the plurality of nanowires is at least one.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The nanowires have a height-to-diameter ratio of at least 1, meaning they are at least as tall as they are wide, ensuring structural integrity.

Claim 9

Original Legal Text

9. The heterostructure of claim 1 , wherein the composite semiconductor layer further includes: a third sub-layer comprising a plurality of nanowires; and a fourth sub-layer immediately adjacent to the third sub-layer, wherein the fourth sub-layer is at least partially continuous.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The composite semiconductor layer *also* includes a third sub-layer with another set of nanowires and a fourth sub-layer immediately adjacent to the third one, where the fourth one is at least partially continuous.

Claim 10

Original Legal Text

10. The heterostructure of claim 9 , wherein the plurality of nanowires of the third sub-layer have at least one characteristic dimension that differs from a corresponding at least one characteristic dimension of the plurality of nanowires of the first sub-layer by at least one percent.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The composite semiconductor layer *also* includes a third sub-layer with another set of nanowires and a fourth sub-layer immediately adjacent to the third one, where the fourth one is at least partially continuous. Critically, at least one size dimension of the nanowires in the first and third layers differs by at least 1%.

Claim 11

Original Legal Text

11. The heterostructure of claim 1 , wherein each of the plurality of nanowires has at least one of: a variable composition or a variable doping.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. Each nanowire has either a variable material composition along its length or is doped with impurities that change along its length.

Claim 12

Original Legal Text

12. The heterostructure of claim 1 , wherein the composite semiconductor layer further includes a template layer, wherein the template layer defines locations of the plurality of nanowires.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The composite semiconductor layer *also* has a template layer that defines where the nanowires are located.

Claim 13

Original Legal Text

13. The heterostructure of claim 12 , wherein the template layer includes a plurality of openings, and wherein the plurality of nanowires are located in the plurality of openings.

Plain English Translation

The heterostructure includes a composite semiconductor layer made of multiple sub-layers. One sub-layer contains nanowires spaced 2-100 nm apart. An adjacent sub-layer has a partially continuous structure with isolated cavities arranged differently from the nanowire spacing. The nanowires contact this second sub-layer but don't go *into* the cavities. The composite semiconductor layer *also* has a template layer that defines where the nanowires are located. The template layer has holes, and the nanowires grow inside these holes.

Claim 14

Original Legal Text

14. An optoelectronic device comprising: a sapphire substrate; and a buffer layer immediately adjacent to the sapphire substrate, wherein the buffer layer is formed of aluminum nitride and includes a plurality of sub-layers formed therein, wherein the plurality of sub-layers includes: a first sub-layer comprising a plurality of nanowires with a characteristic spacing between each of the nanowires that ranges from 2 nm to 100 nm; and a second sub-layer immediately adjacent to the first sub-layer, wherein the second sub-layer includes a partially continuous interior portion with isolated cavities formed therein, the isolated cavities having an arrangement distinct from the spacing between the plurality of nanowires, and wherein the plurality of nanowires of the first sub-layer contact the second sub-layer without penetrating into any of the isolated cavities.

Plain English Translation

An optoelectronic device contains a sapphire substrate with a buffer layer of aluminum nitride (AlN) on top of it. This buffer layer includes two sub-layers: one with nanowires spaced 2-100 nm apart, and the other immediately next to it with a partially continuous structure and isolated cavities arranged differently from the nanowire spacing. The nanowires touch the second sub-layer but don't enter the cavities. This buffer layer configuration reduces stress, enhancing the device's optical properties.

Claim 15

Original Legal Text

15. The device of claim 14 , wherein each of the plurality of nanowires has a characteristic diameter in a range of 5-500 nm, and a characteristic length in a range of 50 nm-5 microns.

Plain English Translation

An optoelectronic device contains a sapphire substrate with a buffer layer of aluminum nitride (AlN) on top of it. This buffer layer includes two sub-layers: one with nanowires spaced 2-100 nm apart, and the other immediately next to it with a partially continuous structure and isolated cavities arranged differently from the nanowire spacing. The nanowires touch the second sub-layer but don't enter the cavities. The diameter of each nanowire is 5-500 nm, and their length is 50 nm - 5 microns.

Claim 16

Original Legal Text

16. The device of claim 14 , further comprising a group III nitride n-type layer immediately adjacent to the buffer layer.

Plain English Translation

An optoelectronic device contains a sapphire substrate with a buffer layer of aluminum nitride (AlN) on top of it. This buffer layer includes two sub-layers: one with nanowires spaced 2-100 nm apart, and the other immediately next to it with a partially continuous structure and isolated cavities arranged differently from the nanowire spacing. The nanowires touch the second sub-layer but don't enter the cavities. A Group III nitride n-type semiconductor layer is grown directly on top of this AlN buffer layer.

Claim 17

Original Legal Text

17. The device of claim 14 , the composite semiconductor layer further comprising a third sub-layer immediately adjacent to the second sub-layer, wherein third sub-layer is essentially continuous.

Plain English Translation

An optoelectronic device contains a sapphire substrate with a buffer layer of aluminum nitride (AlN) on top of it. This buffer layer includes two sub-layers: one with nanowires spaced 2-100 nm apart, and the other immediately next to it with a partially continuous structure and isolated cavities arranged differently from the nanowire spacing. The nanowires touch the second sub-layer but don't enter the cavities. The buffer layer also has a *third* sub-layer immediately next to the porous one, which is a solid, continuous layer.

Claim 18

Original Legal Text

18. A method comprising: growing a composite semiconductor layer including a plurality of sub-layers, wherein the plurality of sub-layers includes: a first sub-layer comprising a plurality of nanowires with a characteristic spacing between each of the nanowires that ranges from 2 nm to 100 nm; and a second sub-layer immediately adjacent to the first sub-layer, wherein the second sub-layer layer includes a partially continuous interior portion with isolated cavities formed therein, the isolated cavities having an arrangement distinct from the spacing between the plurality of nanowires, and wherein the plurality of nanowires of the first sub-layer contact the second sub-layer without penetrating into any of the isolated cavities.

Plain English Translation

A method grows a composite semiconductor layer comprised of sub-layers. A first sub-layer consists of nanowires spaced 2-100 nm apart. A second sub-layer, immediately adjacent to the first, has a partially continuous structure containing isolated cavities that are arranged differently than the nanowire spacing. The nanowires in the first sub-layer contact the second sub-layer but do not penetrate the cavities. This method enables creation of heterostructures for electronic or optoelectronic devices.

Claim 19

Original Legal Text

19. The method of claim 18 , wherein the growing includes growing the first sub-layer using a plurality of growth steps including: epitaxially growing AlN nucleation islands having a target characteristic diameter and a target characteristic spacing using a set of growth conditions promoting Al-species diffusion at the growth surface; and epitaxially growing the plurality of nanowires over the nucleation islands.

Plain English Translation

A method grows a composite semiconductor layer comprised of sub-layers. A first sub-layer consists of nanowires spaced 2-100 nm apart. A second sub-layer, immediately adjacent to the first, has a partially continuous structure containing isolated cavities that are arranged differently than the nanowire spacing. The nanowires in the first sub-layer contact the second sub-layer but do not penetrate the cavities. The first sub-layer is grown by first epitaxially growing AlN nucleation islands with desired diameter and spacing using conditions that favor aluminum diffusion. Then, the nanowires are grown on top of those islands.

Claim 20

Original Legal Text

20. The method of claim 19 , wherein the epitaxially growing AlN nucleation islands includes selecting at least one of: a V/III ratio or a growth temperature based on the target characteristic diameter.

Plain English Translation

A method grows a composite semiconductor layer comprised of sub-layers. A first sub-layer consists of nanowires spaced 2-100 nm apart. A second sub-layer, immediately adjacent to the first, has a partially continuous structure containing isolated cavities that are arranged differently than the nanowire spacing. The nanowires in the first sub-layer contact the second sub-layer but do not penetrate the cavities. The first sub-layer is grown by first epitaxially growing AlN nucleation islands with desired diameter and spacing using conditions that favor aluminum diffusion. Then, the nanowires are grown on top of those islands. Either the ratio of the precursor gasses (V/III ratio) *or* the growth temperature is selected based on the target diameter of the AlN nucleation islands.

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Patent Metadata

Filing Date

October 21, 2014

Publication Date

November 14, 2017

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