A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A magnetic memory comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer having a fixed magnetization; a second magnetic layer having a changeable magnetization and being disposed between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including a third terminal and a fourth terminal, the third terminal being electrically connected to the first magnetic layer; a transistor including fifth and sixth terminals and a control terminal, the fifth terminal being electrically connected to the first terminal; and a circuit electrically connected to the second terminal, the fourth terminal, the sixth terminal, and the control terminal, wherein when information is to be written into the second magnetic layer, the circuit switches on the transistor, applies a reverse bias to the diode, and supplies current between the second terminal and the sixth terminal, and when information is to be read from the second magnetic layer, the circuit switches off the transistor, and supplies current between the second terminal and the fourth terminal.
A magnetic memory cell includes a conductive layer with two terminals and a portion between them. A magnetoresistive element sits on this portion, consisting of a fixed magnetic layer, a changeable magnetic layer separated from the fixed layer by a nonmagnetic layer. A diode connects to the fixed magnetic layer, and a transistor connects to one of the conductive layer terminals. A circuit controls writing and reading data. Writing involves switching on the transistor, reverse biasing the diode, and supplying current between one conductive layer terminal and one transistor terminal. Reading involves switching off the transistor and supplying current between one conductive layer terminal and one diode terminal.
2. The memory according to claim 1 , further comprising: a first wiring electrically connected to the second terminal, and a second wiring electrically connected to the fourth terminal, wherein a direction from a source toward a drain of the transistor intersects with respective directions in which the first wiring and the second wiring extend.
The magnetic memory cell from the previous description includes a first wiring connected to one of the conductive layer terminals and a second wiring connected to one of the diode terminals. The direction from the transistor's source to drain intersects the directions of the first and second wirings. In other words, the transistor and wiring are arranged such that current flow for writing and reading intersects the direction of current flow through the transistor itself.
3. The memory according to claim 1 , wherein the diode is a schottky diode or an MIM diode, the MIM diode having two electrodes with different work functions.
In the magnetic memory cell, the diode connecting to the fixed magnetic layer is either a Schottky diode or a Metal-Insulator-Metal (MIM) diode. The MIM diode consists of two electrodes with differing work functions. This facilitates the diode's function in controlling current flow direction for writing and reading data to/from the magnetoresistive element.
4. The memory according to claim 1 , wherein the diode is a schottky diode having an uneven impurity concentration.
The magnetic memory cell uses a Schottky diode that has an uneven impurity concentration. This uneven concentration can be used to tailor the diode's electrical characteristics, specifically its forward voltage drop and reverse leakage current, optimizing performance for writing and reading data.
5. The magnetic memory according to claim 1 , wherein the transistor is a recessed transistor.
The magnetic memory cell utilizes a recessed transistor. This transistor type allows for a smaller footprint and potentially improved switching characteristics compared to conventional planar transistors, contributing to higher density and performance of the memory cell.
6. The magnetic memory according to claim 1 , further comprising: a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal, wherein the first and third wirings extend in a first direction, and the second and fourth wirings extend in a second direction.
The magnetic memory cell incorporates a first wiring connected to one of the conductive layer terminals, a second wiring connected to one of the diode terminals, a third wiring connected to one of the transistor terminals, and a fourth wiring connected to the transistor's control terminal. The first and third wirings extend in one direction, while the second and fourth wirings extend in a different direction. This wiring configuration likely facilitates row and column addressing within a memory array.
7. The magnetic memory according to claim 1 , further comprising: a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal, wherein a direction in which the first wiring extends intersects with respective directions in which the second and fourth wirings extend, and a direction in which the third wiring intersects with respective directions in which the second and fourth wirings extend.
The magnetic memory cell incorporates a first wiring connected to one of the conductive layer terminals, a second wiring connected to one of the diode terminals, a third wiring connected to one of the transistor terminals and a fourth wiring connected to the transistor's control terminal. The first wiring intersects the second and fourth wirings, and the third wiring also intersects the second and fourth wirings. This wiring scheme provides a different configuration for row/column addressing compared to claim 6, possibly optimized for a different array layout.
8. The magnetic memory according to claim 1 , wherein the circuit includes a first circuit electrically connected to the fourth terminal and the control terminal, and a second circuit electrically connected to the second terminal and the sixth terminal.
The circuit in the magnetic memory cell is divided into two parts: a first circuit connected to the diode terminal and the transistor's control terminal, and a second circuit connected to one of the conductive layer terminals and one of the transistor terminals. The first circuit likely handles diode biasing and transistor switching, while the second circuit controls current flow for writing and reading operations.
9. A magnetic memory comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer having a fixed magnetization; a second magnetic layer having a changeable magnetization and being disposed between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a bidirectional diode including a third terminal and a fourth terminal, the third terminal being electrically connected to the first magnetic layer; a transistor including fifth and sixth terminals and a control terminal, the fifth terminal being electrically connected to the first terminal; and a circuit electrically connected to the second terminal, the fourth terminal, the sixth terminal, and the control terminal, wherein when information is to be written into the second magnetic layer, the circuit switches on the transistor, applies a voltage equal to or less than a threshold value to the bidirectional diode, and supplies current between the second terminal and the sixth terminal, and when information is to be read from the second magnetic layer, the circuit switches off the transistor, and supplies current between the second terminal and the fourth terminal.
A magnetic memory cell includes a conductive layer with two terminals and a portion between them. A magnetoresistive element sits on this portion, consisting of a fixed magnetic layer, a changeable magnetic layer separated from the fixed layer by a nonmagnetic layer. A bidirectional diode connects to the fixed magnetic layer, and a transistor connects to one of the conductive layer terminals. A circuit controls writing and reading data. Writing involves switching on the transistor, applying a voltage equal to or less than a threshold value to the bidirectional diode, and supplying current between one conductive layer terminal and one transistor terminal. Reading involves switching off the transistor and supplying current between one conductive layer terminal and one diode terminal.
10. The memory according to claim 9 , further comprising: a first wiring electrically connected to the second terminal and a second wiring electrically connected to the fourth terminal, wherein a direction from a source toward a drain of the transistor intersects with respective directions in which the first wiring and the second wiring extend.
The magnetic memory cell from the previous description utilizes a first wiring connected to one of the conductive layer terminals, and a second wiring connected to one of the diode terminals. The direction from the transistor's source to drain intersects with the directions in which the first and second wirings extend. This orthogonal arrangement affects current flow patterns within the memory cell during read and write operations.
11. The magnetic memory according to claim 9 , wherein the transistor is a recessed transistor.
In this magnetic memory cell design, the transistor is a recessed transistor. Using a recessed transistor can lead to advantages like a smaller cell size, improved switching speeds, and potentially lower power consumption compared to using a standard planar transistor.
12. The magnetic memory according to claim 9 , further comprising: a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal, wherein the first and third wirings extend in a first direction, and the second and fourth wirings extend in a second direction.
The magnetic memory cell includes a first wiring connected to one of the conductive layer terminals, a second wiring connected to one of the diode terminals, a third wiring connected to one of the transistor terminals, and a fourth wiring connected to the control terminal of the transistor. The first and third wirings extend in a first direction, while the second and fourth wirings extend in a second direction. This wiring configuration is likely designed to optimize the layout and routing of signals within a memory array built from these cells.
13. The magnetic memory according to claim 9 , further comprising: a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal, wherein a direction in which the first wiring extends intersects with respective directions in which the second and fourth wirings extend, and a direction in which the third wiring intersects with respective directions in which the second and fourth wirings extend.
The magnetic memory cell has a first wiring connected to one of the conductive layer terminals, a second wiring connected to one of the diode terminals, a third wiring connected to one of the transistor terminals, and a fourth wiring connected to the control terminal of the transistor. The direction of the first wiring intersects the directions of the second and fourth wirings, and the direction of the third wiring also intersects the directions of the second and fourth wirings. This specific arrangement of wiring is used to control the flow of signals and power within the memory array architecture.
14. The magnetic memory according to claim 9 , wherein the circuit includes a first circuit electrically connected to the fourth terminal and the control terminal, and a second circuit electrically connected to the second terminal and the sixth terminal.
The circuit in this magnetic memory cell is composed of two parts. The first circuit connects to the diode terminal and the control terminal of the transistor. The second circuit connects to one of the conductive layer terminals and one of the transistor terminals. The first circuit likely manages the biasing and switching behavior of the diode and transistor, while the second circuit handles current supply during writing and reading operations.
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September 15, 2016
November 28, 2017
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