There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
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1. A semiconductor structure, comprising: a substrate; a transition body over said substrate; a group III-V intermediate body having a bottom surface over said transition body; a group III-V device layer over a top surface of said group III-V intermediate body; wherein said group III-V intermediate body has an impurity concentration that is substantially constant from said bottom surface to a first intermediate depth between said bottom surface and said top surface, reduces at a substantially constant rate as a function of position from said first intermediate depth to a second intermediate depth between said first intermediate depth and said top surface, and is substantially constant from said second intermediate depth to said top surface.
A semiconductor device structure includes a substrate, a transition layer on the substrate, a Group III-V material layer (like GaN) on the transition layer, and a Group III-V device layer on the Group III-V material layer. The Group III-V material layer has a specific impurity profile: the impurity concentration is constant from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface. This creates a continuously reduced impurity concentration profile with three distinct sections.
2. The semiconductor structure of claim 1 , wherein an impurity producing said impurity concentration is a P type impurity.
The semiconductor device structure, as previously described, has a Group III-V material layer where the impurity that is concentration-controlled is a P-type impurity. Therefore, the Group III-V material layer has a constant P-type impurity concentration from its bottom to a certain depth, then the P-type impurity concentration decreases at a constant rate to another depth closer to the top, and finally, the P-type impurity concentration is constant again from that second depth to the top surface.
3. The semiconductor structure of claim 1 , wherein said impurity concentration comprises a carbon concentration.
The semiconductor device structure, as previously described, has a Group III-V material layer where the impurity whose concentration is controlled is carbon. Therefore, the Group III-V material layer has a constant carbon concentration from its bottom to a certain depth, then the carbon concentration decreases at a constant rate to another depth closer to the top, and finally, the carbon concentration is constant again from that second depth to the top surface.
4. The semiconductor structure of claim 1 , wherein said impurity concentration includes a plurality of impurity species.
The semiconductor device structure, as previously described, has a Group III-V material layer where the controlled impurity concentration is composed of several different impurity types. Therefore, the combined concentration of several different impurities is constant from the Group III-V material layer's bottom to a certain depth, then the combined impurity concentration decreases at a constant rate to another depth closer to the top, and finally, the combined impurity concentration is constant again from that second depth to the top surface.
5. The semiconductor structure of claim 1 , wherein said group III-V intermediate body comprises a compositionally graded III-Nitride body having a first III-Nitride composition at said bottom surface and a second III-Nitride composition above said bottom surface.
The semiconductor device structure, as previously described, has a Group III-V material layer made of a III-Nitride material (like GaN) where the composition changes gradually throughout the layer. The III-Nitride material has one composition at its bottom surface and another composition at a location above the bottom surface. Furthermore, the impurity concentration is constant from the Group III-V material layer's bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
6. The semiconductor structure of claim 1 , wherein said transition body includes a group III-V transition structure having a selectively modified impurity concentration such that a bottom surface impurity concentration of said group III-V transition structure is selectively modified to a top surface impurity concentration of said group III-V transition structure.
The semiconductor device structure, as previously described, includes a transition layer made of a Group III-V material that also has a controlled impurity concentration. The transition layer's impurity concentration is modified from the bottom to the top surface. Therefore, the Group III-V material layer has a constant impurity concentration from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
7. The semiconductor structure of claim 6 , wherein said selectively modified impurity concentration is modified in a step-wise fashion from said bottom surface impurity concentration to said top surface impurity concentration.
The semiconductor device structure, as previously described, includes a transition layer made of a Group III-V material with a controlled impurity concentration. The transition layer's impurity concentration changes in steps from the bottom to the top surface. Furthermore, the Group III-V material layer has a constant impurity concentration from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
8. The semiconductor structure of claim 6 , wherein said selectively modified impurity concentration rises and falls between said bottom surface impurity concentration and said top surface impurity concentration.
The semiconductor device structure, as previously described, includes a transition layer made of a Group III-V material with a controlled impurity concentration. The transition layer's impurity concentration rises and falls between its bottom and top surfaces. Furthermore, the Group III-V material layer has a constant impurity concentration from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
9. A method, comprising: fabricating a transition body over a substrate; fabricating a group III-V intermediate body having a bottom surface over said transition body; fabricating a group III-V device layer over a top surface of said group III-V intermediate body; wherein fabricating said group III-V intermediate body comprises reducing an impurity concentration of said group III-V intermediate body such that said impurity concentration is substantially constant from said bottom surface to a first intermediate depth between said bottom surface and said top surface, reduces at a substantially constant rate as a function of position from said first intermediate depth to a second intermediate depth between said first intermediate depth and said top surface, and is substantially constant from said second intermediate depth to said top surface.
A method for making a semiconductor device: First, create a transition layer on a substrate. Then, create a Group III-V material layer (like GaN) on the transition layer. Finally, create a Group III-V device layer on the Group III-V material layer. When creating the Group III-V material layer, reduce the impurity concentration in a specific way: the impurity concentration is constant from the bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
10. The method of claim 9 , wherein fabricating said group III-V intermediate body comprises selectively reducing a growth rate of said group HI-V intermediate body from a higher growth rate at said bottom surface to a lower growth rate at said top surface.
The method of fabricating a semiconductor device, as previously described, involves creating the Group III-V material layer by changing the growth rate from bottom to top. The growth rate is higher at the bottom and lower at the top of the Group III-V material layer. Furthermore, the impurity concentration is constant from the Group III-V material layer's bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
11. The method of claim 9 , wherein fabricating said group III-V intermediate body comprises selectively increasing a growth temperature of said group III-V intermediate body from a lower growth temperature at said bottom surface to a higher growth temperature at said top surface.
The method of fabricating a semiconductor device, as previously described, involves creating the Group III-V material layer by changing the growth temperature from bottom to top. The growth temperature is lower at the bottom and higher at the top of the Group III-V material layer. Furthermore, the impurity concentration is constant from the Group III-V material layer's bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
12. The method of claim 9 , wherein an impurity producing said impurity concentration is a P type impurity.
The method of fabricating a semiconductor device, as previously described, involves creating the Group III-V material layer where the impurity being controlled is a P-type impurity. Furthermore, the impurity concentration is constant from the Group III-V material layer's bottom to a certain depth, then the P-type impurity concentration decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
13. The method of claim 9 , wherein said impurity concentration comprises a carbon concentration.
The method of fabricating a semiconductor device, as previously described, involves creating the Group III-V material layer where the impurity being controlled is carbon. Furthermore, the carbon concentration is constant from the Group III-V material layer's bottom to a certain depth, then the carbon concentration decreases at a constant rate to another depth closer to the top, and finally, the carbon concentration is constant again from that second depth to the top surface.
14. The method of claim 9 , wherein said impurity concentration includes a plurality of impurity species.
The method of fabricating a semiconductor device, as previously described, involves creating the Group III-V material layer where the controlled impurity concentration is composed of several different impurity types. Furthermore, the combined concentration of several different impurities is constant from the Group III-V material layer's bottom to a certain depth, then the combined impurity concentration decreases at a constant rate to another depth closer to the top, and finally, the combined impurity concentration is constant again from that second depth to the top surface.
15. The method of claim 9 , wherein said group III-V intermediate body comprises a compositionally graded III-Nitride body having a first III-Nitride composition at said bottom surface and a second III-Nitride composition above said bottom surface.
The method of fabricating a semiconductor device, as previously described, involves creating the Group III-V material layer made of a III-Nitride material (like GaN) where the composition changes gradually throughout the layer. The III-Nitride material has one composition at its bottom surface and another composition at a location above the bottom surface. Furthermore, the impurity concentration is constant from the Group III-V material layer's bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
16. The method of claim 9 , wherein fabricating said transition body includes fabricating a group III-V transition structure having a selectively modified impurity concentration such that a bottom surface impurity concentration of said group IH-V transition structure is selectively modified to a top surface impurity concentration of said group III-V transition structure.
The method of fabricating a semiconductor device, as previously described, includes creating a transition layer made of a Group III-V material that also has a controlled impurity concentration. The transition layer's impurity concentration is modified from the bottom to the top surface. Furthermore, the impurity concentration of the Group III-V material layer is constant from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
17. The method of claim 16 , wherein said selectively modified impurity concentration is reduced in a step-wise fashion from said bottom surface impurity concentration to said top surface impurity concentration.
The method of fabricating a semiconductor device, as previously described, includes creating a transition layer made of a Group III-V material with a controlled impurity concentration. The transition layer's impurity concentration changes in steps from the bottom to the top surface. Furthermore, the impurity concentration of the Group III-V material layer is constant from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
18. The method of claim 16 , wherein said selectively modified impurity concentration rises and falls between said bottom surface impurity concentration and said top surface impurity concentration.
The method of fabricating a semiconductor device, as previously described, includes creating a transition layer made of a Group III-V material with a controlled impurity concentration. The transition layer's impurity concentration rises and falls between its bottom and top surfaces. Furthermore, the impurity concentration of the Group III-V material layer is constant from its bottom to a certain depth, then it decreases at a constant rate to another depth closer to the top, and finally, the impurity concentration is constant again from that second depth to the top surface.
19. A semiconductor structure, comprising: a substrate; a transition body over said substrate; a group III-V intermediate body having a bottom surface over said transition body; a group III-V device layer over a top surface of said group III-V intermediate body; wherein said group III-V intermediate body comprises an impurity concentration having at least two step-wise reductions in a direction from said bottom surface to said top surface.
A semiconductor device structure includes a substrate, a transition layer on the substrate, a Group III-V material layer (like GaN) on the transition layer, and a Group III-V device layer on the Group III-V material layer. The Group III-V material layer has an impurity concentration that decreases from the bottom to the top in at least two steps, creating at least two distinct plateaus of impurity concentration.
20. The semiconductor structure of claim 19 , wherein said impurity concentration has at least four step-wise reductions in said direction from said bottom surface to said top surface.
The semiconductor device structure, as previously described, has a Group III-V material layer with an impurity concentration profile that decreases in at least four steps from bottom to top. This creates at least four distinct plateaus where the impurity concentration is reduced step-wise throughout the layer.
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January 31, 2017
November 28, 2017
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