To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.
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1. A method of manufacturing a semiconductor device comprising the steps of: (a) preparing a semiconductor substrate that includes a first pad electrode and a second pad electrode, the first pad electrode being formed at an uppermost layer of a plurality of wiring layers and having a first metal film formed on a surface of the first pad electrode, and the second pad electrode being electrically connected to the first pad electrode, being formed at the uppermost layer of the plurality of wiring layers and having a second metal film formed on a surface of the second pad electrode; (b) forming a first insulating film having a first opening for exposing the first metal film in the first pad electrode, and a second opening for exposing the second metal film in the second pad electrode; (c) forming a mask layer on the first insulating film for covering the first opening and exposing the second opening; (d) forming a wiring which is electrically connected to the second pad electrode via the second opening; (e) forming a second insulating film on the first pad electrode and on the wiring; (f) forming a third opening in the second insulating film above the first pad electrode and forming a fourth opening of the second insulating film above the wiring while leaving an organic reaction layer on each surface of the first pad electrode and the wiring; (g) performing heat processing on the semiconductor substrate after the step (f), while maintaining the organic reaction layer on each surface of the first pad electrode and the wiring; and (h) forming a bump on the wiring in the fourth opening.
A method for manufacturing semiconductor devices improves reliability by reducing solder bonding defects. It involves: (a) preparing a semiconductor wafer with a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; (b) forming an insulating film with openings to expose these metal films; (c) using a mask to cover the first opening and expose the second; (d) creating a wiring connected to the second pad through its opening; (e) forming a second insulating film on the first pad and the new wiring; (f) etching openings in the second insulating film above the first pad and wiring, leaving an organic reaction layer on both surfaces; (g) heat treating the wafer while keeping these organic layers intact; and (h) forming a bump on the wiring within its opening.
2. The method of manufacturing the semiconductor device according to claim 1 , wherein the first opening is exposed by removing the mask layer, and further, a conductive layer on the first metal film is removed by etching while leaving the first metal film of the first pad electrode after the step (d).
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. After forming the wiring electrically connected to the second pad electrode via the second opening, the mask layer is removed to expose the first opening, and then the conductive layer on the first metal film is etched away, but the first metal film itself is left intact.
3. The method of manufacturing the semiconductor device according to claim 2 , wherein the conductive layer is formed of a different material from the first metal film.
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; a bump is formed on the wiring; and where the mask is removed and a conductive layer etched from the first metal film of the first pad electrode after wiring formation. Specifically, the conductive layer that is etched away is made from a different material than the first metal film itself.
4. The method of manufacturing the semiconductor device according to claim 1 , wherein a temperature of the heat processing in the step (g) is higher than a melting point of the bump.
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. The heat processing step is performed at a temperature higher than the melting point of the bump material, ensuring good connection.
5. The method of manufacturing the semiconductor device according to claim 1 , further comprising performing a first probe test by bringing a probe needle in contact with the first pad electrode between the step (f) and the step (g).
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. Before heat processing but after forming the openings above the pads and wiring, a probe test is performed by physically contacting the first pad electrode with a probe needle to test its functionality.
6. The method of manufacturing the semiconductor device according to claim 1 , further comprising performing a second probe test by bringing a probe needle in contact with the first pad electrode after the step (g), while maintaining the organic reaction layer on each surface of the first pad electrode and the wiring.
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. After the heat processing step, a second probe test is conducted by contacting the first pad electrode with a probe needle. This test is done while the organic reaction layer is still present on the pad and wiring surfaces.
7. The method of manufacturing the semiconductor device according to claim 1 , further comprising removing the organic reaction layer from the surface of the wiring after the step (g) before the step (h).
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. Before forming the bump on the wiring, the organic reaction layer is removed from the wiring surface.
8. The method of manufacturing the semiconductor device according to claim 1 , wherein the heat processing in the step (g) is a baking test of a non-volatile memory which is formed in a region of a semiconductor chip of the semiconductor substrate.
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. The heat processing is specifically a baking test used for non-volatile memory devices fabricated on the semiconductor chip.
9. The method of manufacturing the semiconductor device according to claim 1 , wherein a size of the first opening viewed in a plan view is larger than a size of the second opening viewed in a plan view.
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. The size of the opening above the first pad electrode is larger than the size of the opening above the second pad electrode, when viewed from above.
10. The method of manufacturing the semiconductor device according to claim 1 , further comprising: after step (h), dicing the semiconductor substrate to form the semiconductor device including the first pad electrode, the second pad electrode, and the bump on the wiring to electrically connect to the first and second pad electrodes.
This semiconductor manufacturing method builds upon the method where a semiconductor wafer has a first and second pad electrode on the uppermost wiring layer, each with a metal film on the surface; an insulating film has openings exposing these metal films; a mask covers the first opening and exposes the second; a wiring connects to the second pad; a second insulating film is formed on the first pad and wiring; etching creates openings above the first pad and wiring, leaving an organic reaction layer; heat treatment is performed; and a bump is formed on the wiring. After the bump is formed, the semiconductor wafer is diced to separate the individual semiconductor devices. Each device then includes the first pad electrode, the second pad electrode, and the bump on the wiring providing an electrical connection between them.
11. A semiconductor device comprising: a semiconductor chip having a main surface in which a semiconductor circuit is formed; a plurality of first pad electrodes electrically connected to the semiconductor circuit and covered by a plurality of metal films, respectively; a plurality of second pad electrodes electrically connected to the plurality of first pad electrodes, respectively, and formed on the same layer with each of the plurality of first pad electrodes; a plurality of wirings covering each of the plurality of second pad electrodes and electrically connected to the plurality of second pad electrodes, respectively; an insulating film formed on the plurality of wirings; and a plurality of bumps provided in opening portions of the respective insulating films of the plurality of wirings, wherein each surface of the plurality of metal films is exposed and each metal film has a hole piercing therethrough.
A semiconductor device contains a chip with a circuit on its surface, multiple first pad electrodes connected to the circuit and covered by respective metal films with holes through them, and second pad electrodes (on the same layer as the first pads) that are also connected to the first pads. Wirings cover and connect to the second pad electrodes. An insulating film sits atop the wirings, and bumps are located in openings within this film above the wiring. The metal films on the first pad electrodes are exposed.
12. The semiconductor device according to claim 11 , wherein each metal film extends on one of the plurality of second pad electrodes.
This semiconductor device contains a chip with a circuit on its surface, multiple first pad electrodes connected to the circuit and covered by respective metal films with holes through them, and second pad electrodes (on the same layer as the first pads) that are also connected to the first pads. Wirings cover and connect to the second pad electrodes. An insulating film sits atop the wirings, bumps are located in openings within this film, the metal films on the first pad electrodes are exposed, and all where each metal film that covers a first pad extends partially onto one of the second pad electrodes.
13. The semiconductor device according to claim 11 , wherein each of the plurality of first pad electrodes is arranged on an end portion side of the semiconductor chip, each of the plurality of second pad electrodes is arranged at an inner side than each of the plurality of first pad electrodes, and the wiring is led out from each of the plurality of second pad electrodes arranged at the inner side.
This semiconductor device contains a chip with a circuit on its surface, multiple first pad electrodes connected to the circuit and covered by respective metal films with holes through them, and second pad electrodes (on the same layer as the first pads) that are also connected to the first pads. Wirings cover and connect to the second pad electrodes. An insulating film sits atop the wirings, bumps are located in openings within this film, the metal films on the first pad electrodes are exposed, and all where the first pad electrodes are placed along the edge of the chip, and the second pad electrodes are located further inward, with the wiring leading out from these inner pads.
14. The semiconductor device according to claim 11 , wherein the semiconductor circuit includes a non-volatile memory circuit.
This semiconductor device contains a chip with a non-volatile memory circuit on its surface, multiple first pad electrodes connected to the circuit and covered by respective metal films with holes through them, and second pad electrodes (on the same layer as the first pads) that are also connected to the first pads. Wirings cover and connect to the second pad electrodes. An insulating film sits atop the wirings, bumps are located in openings within this film, the metal films on the first pad electrodes are exposed.
15. The semiconductor device according to claim 11 , further comprising a plurality of metal wires including ends connected to the plurality of first pad electrodes, respectively, portions of plurality of metal wires spaced-apart from the semiconductor chip.
This semiconductor device contains a chip with a circuit on its surface, multiple first pad electrodes connected to the circuit and covered by respective metal films with holes through them, and second pad electrodes (on the same layer as the first pads) that are also connected to the first pads. Wirings cover and connect to the second pad electrodes. An insulating film sits atop the wirings, bumps are located in openings within this film, the metal films on the first pad electrodes are exposed. Additionally, metal wires have ends connected to the first pad electrodes but are otherwise spaced apart from the chip's surface.
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August 24, 2016
December 5, 2017
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