Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming an integrated circuit (IC) structure, the method comprising: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer and semiconductor materials from the conductive epitaxial layer into the boron etch-stop layer, such that the boron etch-stop layer and a portion of the conductive epitaxial layer become a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.
2. The method of claim 1 , further comprising forming a silicide region within the boron-rich region after the annealing.
3. The method of claim 1 , wherein the semiconductor element includes a semiconductor fin positioned on an insulator of a semiconductor-on-insulator (SOI) structure.
4. The method of claim 1 , wherein the boron etch-stop layer consists of boron.
5. The method of claim 1 , wherein the conductive epitaxial layer includes boron and silicon germanium.
6. The method of claim 1 , wherein the annealing occurs after the forming of the opening within the insulator.
7. The method of claim 6 , wherein the boron-rich region includes a substantially uniform boron concentration after the annealing.
8. The method of claim 1 , wherein the forming of boron stop layer includes depositing the boron etch-stop layer using a process selected from the group consisting of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD).
9. The method of claim 1 , wherein a thickness of the boron etch-stop layer is between approximately two nanometers and five nanometers.
10. The method of claim 1 , further comprising forming a gate structure on the semiconductor element before forming the conductive epitaxial layer, the gate structure including a set of sidewall spacers, and wherein the conductive epitaxial layer laterally abuts a sidewall spacer of the gate structure after the growing.
11. A method of forming an integrated circuit (IC) structure, the method comprising: growing a conductive epitaxial layer on at least one semiconductor fin; forming a boron etch-stop layer directly on the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer and semiconductor materials from the conductive epitaxial layer into the boron etch-stop layer, such that the boron etch-stop layer and a portion of the conductive epitaxial layer become a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the at least one semiconductor fin through at least the conductive epitaxial layer.
12. The method of claim 11 , further comprising forming a silicide region within the boron-rich region after the annealing.
13. The method of claim 11 , wherein the boron etch-stop layer consists of boron.
14. The method of claim 11 , wherein the conductive epitaxial layer includes boron and silicon germanium.
15. The method of claim 11 , wherein the annealing occurs after the forming of the opening within the insulator, and wherein the boron-rich region includes a substantially uniform boron concentration after the annealing.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 18, 2016
December 12, 2017
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.