A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A controller comprising: a storage device to store instructions; and a processing device to execute the instructions stored in the storage device to: reset at least one first memory device on a first rank and at least one second memory device on a second rank based at least in part on a reset signal encoded in a first command/address signal and in a second command/address signal and transmitted to the at least one first memory device and to the at least one second memory device; assign a first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assign a second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal based at least in part on an assignment signal encoded in the second command/address signal and transmitted to the at least one first memory device and to the at least one second memory device; and select the first rank or the second rank based at least in part on a selection signal encoded in the first command/address signal and transmitted to the at least one first memory device and to the at least one second memory device.
2. The controller of claim 1 , wherein the processing device executes the instructions stored in the storage device further to: transmit the reset signal to the first terminal and to the second terminal of the at least one first memory device; and transmit the reset signal to the first terminal and to the second terminal of the at least one second memory device.
3. The controller of claim 2 , wherein the processing device executes the instructions stored in the storage device further to: transmit the assignment signal to the second terminal of the at least one first memory device; and transmit the assignment signal to the first terminal of the at least one second memory device.
4. The controller of claim 3 , wherein the processing device executes the instructions stored in the storage device further to: transmit the selection signal to the first terminal of the at least one first memory device; and transmit the selection signal to the second terminal of the at least one second memory device.
5. A computer-readable storage medium having instructions stored thereon that, in response to execution by a processing device, causes the processing device to perform operations comprising: resetting at least one first memory device on a first rank and at least one second memory device on a second rank by encoding a reset signal in a first command/address signal and in a second command/address signal and transmitting the reset signal to the at least one first memory device and to the at least one second memory device; assigning a first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assigning a second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal by encoding an assignment signal in the second command/address signal and transmitting the assignment signal to the at least one first memory device and to the at least one second memory device; and selecting the first rank or the second rank by encoding a selection signal in the first command/address signal and transmitting the selection signal to the at least one first memory device and to the at least one second memory device.
6. The computer-readable storage medium of claim 5 , wherein execution of the instructions causes the processing device to perform operations further comprising: transmitting the reset signal to the first terminal and to the second terminal of the at least one first memory device; and transmitting the reset signal to the first terminal and to the second terminal of the at least one second memory device.
7. The computer-readable storage medium of claim 6 , wherein execution of the instructions causes the processing device to perform operations further comprising: transmitting the assignment signal to the second terminal of the at least one first memory device; and transmitting the assignment signal to the first terminal of the at least one second memory device.
8. The computer-readable storage medium of claim 7 , wherein execution of the instructions causes the processing device to perform operations further comprising: transmitting the selection signal to the first terminal of the at least one first memory device; and transmitting the selection signal to the second terminal of the at least one second memory device.
9. A method comprising: resetting at least one first memory device on a first rank and at least one second memory device on a second rank by encoding a reset signal in a first command/address signal and in a second command/address signal and transmitting the reset signal to the at least one first memory device and to the at least one second memory device; assigning a first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assigning a second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal by encoding an assignment signal in the second command/address signal and transmitting the assignment signal to the at least one first memory device and to the at least one second memory device; and selecting the first rank or the second rank by encoding a selection signal in the first command/address signal and transmitting the selection signal to the at least one first memory device and to the at least one second memory device.
10. The method of claim 9 , further comprising: transmitting the reset signal to the first terminal and to the second terminal of the at least one first memory device; and transmitting the reset signal to the first terminal and to the second terminal of the at least one second memory device.
11. The method of claim 10 , further comprising: transmitting the assignment signal to the second terminal of the at least one first memory device; and transmitting the assignment signal to the first terminal of the at least one second memory device.
12. The method of claim 1 , further comprising: transmitting the selection signal to the first terminal of the at least one first memory device; and transmitting the selection signal to the second terminal of the at least one second memory device.
13. A system comprising: a first rank comprising at least one first memory device including a first input terminal and a second input terminal; a second rank comprising at least one second memory device including a first input terminal and a second input terminal; and a controller configured to: reset that at least one first memory device of the first rank and that at least one second memory device of the second rank based at least in part on a reset signal encoded in a first command/address signal and in a second command/address signal and transmitted to the at least one first memory device and to the at least one second memory device; assign the first terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal and assign the second terminal of the at least one first memory device or of the at least one second memory device to receive the first command/address signal or the second command/address signal based at least in part on an assignment signal encoded in the second command/address signal and transmitted to the at least one first memory device and to the at least one second memory device; and select the first rank or the second rank based at least in part on a selection signal encoded in the first command/address signal and transmitted to the at least one first memory device and to the at least one second memory device.
14. The system of claim 13 , the controller further configured to: transmit the reset signal to the first terminal and to the second terminal of the at least one first memory device; and transmit the reset signal to the first terminal and to the second terminal of the at least one second memory device.
15. The system of claim 14 , the controller further configured to: transmit the assignment signal to the second terminal of the at least one first memory device; and transmit the assignment signal to the first terminal of the at least one second memory device.
16. The system of claim 15 , the controller further configured to: transmit the selection signal to the first terminal of the at least one first memory device; and transmit the selection signal to the second terminal of the at least one second memory device.
17. The system of claim 13 , the controller further comprises a data terminal configured to transmit a data signal to the at least one of the first memory device or the at least one second memory device.
18. The system of claim 13 , further comprising: a printed circuit board housing the first rank, the second rank, and the controller, the printed circuit board having: a first command/address signal trace routed on a first side or a first layer of the printed circuit board from a first controller terminal of the controller to the first input terminal of the at least one first memory device and routed on a second side or a second layer of the printed circuit board from the first controller terminal to the second input terminal of the at least one second memory device; and a second command/address signal trace routed on the first side or the first layer of the printed circuit board from a second controller terminal of the controller to the second input terminal of the at least one first memory device and routed on the second side or the second layer of the printed circuit board from the second controller terminal to the first input terminal of the at least one second memory device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 21, 2017
December 26, 2017
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