Power saving techniques in computing devices

More than one reissue application has been filed for the resissue of U.S. Pat. No. 9,535,490. The reissue applications are the present application and U.S. patent application Ser. No. 17/387,544, which are both continuation reissues of U.S. patent application Ser. No. 17/240,496 filed on Apr. 26, 2021, and entitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which is an application for reissue of U.S. Pat. No. 9,535,490.

Thepresent applicationU.S. Pat. No. 9,535,490claims priority to U.S. Provisional Patent Application Ser. No. 61/916,498 filed on Dec. 16, 2013 and entitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which is incorporated herein by reference in its entirety.

Thepresent applicationU.S. Pat. No. 9,535,490also claims priority to U.S. Provisional Patent Application Ser. No. 62/019,073 filed on Jun. 30, 2014 and entitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which is incorporated herein by reference in its entirety.

I. Field of the Disclosure

The technology of the disclosure relates generally to power saving techniques in computing devices.

II. Background

Computing devices are common within modem society. Ranging from small, mobile computing devices, such as a smart phone or tablet, to large server farms with numerous blades and memory banks, these devices are expected to communicate across myriad networks while providing various other base functions. While desktop devices and servers are generally immune to concerns about power consumption, mobile devices constantly struggle to find a proper balance between available functions and battery life. That is, as more functions are provided, power consumption increases, and battery life is shortened. Servers may likewise have power consumption concerns when assembled in large server farms.

Concurrent with power consumption concerns, improvements in network communications have increased data rates. For example, copper wires have been replaced with higher bandwidth fiber optic cables, and cellular networks have evolved from early Advanced Mobile Phone System (AMPS) and Global System for Mobile Communications (GSM) protocols to 4G and Long Term Evolution (LTE) protocols capable of supporting much higher data rates. As the data rates have increased, the need to be able to process these increased data rates within computing devices has also increased. Thus, earlier mobile computing devices may have had internal buses formed according to a High Speed Inter-Chip (HSIC) standard, universal serial bus (USB) standard (and particularly USB 2.0), or universal asynchronous receiver/transmitter (UART) standard. However, these buses do not support current data rates.

In response to the need for faster internal buses, the peripheral component interconnect express (PCIe) standard, as well as, later generations of USB (e.g., USB 3.0 and subsequent versions) have been adopted for some mobile computing devices. However, while PCIe and USB 3.0 can handle the high data rates currently being used, usage of such buses results in excessive power consumption and negatively impacts battery life by shortening the time between recharging events.

Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset. By holding or accumulating the data at a source processor in this fashion, unnecessary transitions between low power states and active states on the PCIe bus are reduced and power is conserved.

In an alternate aspect, instead of initiating data transfer based on the expiration of the downlink timer (with or without expiration of the uplink timer), accumulated data transfer may be initiated based on expiration of just an uplink accumulation timer. The uplink accumulation timer may be within a host or a device associated with the interconnectivity bus.

In another alternate aspect, initiation of the data transfer may be based on reaching a predefined threshold for a byte accumulation limit counter. The byte accumulation limit counter is not mutually exclusive relative to the other counters and may operate as an override mechanism for one of the other accumulation timers. Use of such an override may be useful in situations where a sudden burst of data arrives that would exceed buffer space and/or bus bandwidth. Likewise, instead of a byte counter, a packet size counter or a “total number of packets” counter may be used to cover situations where numerous packets or a particularly large packet is delivered by the network.

In further aspects of the present disclosure, the timers may be overridden by other factors or parameters. Such an override is alluded to above with the byte accumulation limit counters and the total number of packets counter, which causes data transfers independently of the timers. Other parameters may also override the timers, such as the presence of low latency traffic (e.g., control messages), synchronizing the uplink and downlink data transfers, or low latency quality of service requirements. When such traffic is present, an interrupt or other command may be used to initiate data transfers before expiration of a timer. Still other factors may override the timers, such as an indication that a device or host is not in an automatic polling mode.

In this regard in one aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem timer. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until expiration of the modem timer. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until receipt of the modem processor to application processor data from the modem processor through the interconnectivity bus after which the application processor to modem processor data is sent to the modem processor through the interconnectivity bus.

In another aspect, a method of controlling power consumption in a computing device is disclosed. The method comprises holding data received by a modem processor from a remote network until expiration of a downlink timer. The method also comprises passing the data received by the modem processor to an application processor over an interconnectivity bus. The method also comprises holding application data generated by an application associated with the application processor for until receipt of the data from the modem processor or expiration of an uplink timer, whichever occurs first.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem processor. The mobile terminal also comprises an application timer. The mobile terminal also comprises an application processor. The application processor is configured to hold application processor to modem processor data until expiration of the application timer. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The modem processor is configured to hold modem processor to application processor data until receipt of the application processor to modem processor data from the application processor through the interconnectivity bus after which the modem processor to application processor data is sent to the application processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem byte accumulation limit counter. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until a predefined threshold of bytes has been reached by the modem byte accumulation limit counter. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until receipt of the modem processor to application processor data from the modem processor through the interconnectivity bus after which the application processor to modem processor data is sent to the modem processor through the interconnectivity bus.

With regards to another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem packet counter. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until a predefined threshold of packets has been reached by the modem packet counter. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until receipt of the modem processor to application processor data from the modem processor through the interconnectivity bus after which the application processor to modem processor data is sent to the modem processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem processor. The mobile terminal also comprises an application byte counter. The mobile terminal also comprises an application processor. The application processor is configured to hold application processor to modem processor data until a predefined threshold of bytes has been reached by the application byte counter. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The modem processor is configured to hold modem processor to application processor data until receipt of the application processor to modem processor data from the application processor through the interconnectivity bus after which the modem processor to application processor data is sent to the application processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem processor and an application packet counter. The mobile terminal also comprises an application processor. The application processor is configured to hold application processor to modem processor data until a predefined threshold of packets has been reached by the application packet counter. The mobile terminal comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The modem processor is configured to hold the modem processor to application processor data until receipt of the application processor to modem processor data from the application processor through the interconnectivity bus after which the modem processor to application processor data is sent to the application processor through the interconnectivity bus.

With regards to another aspect, a method is disclosed. The method comprises starting an application timer at an application processor. The method also comprises accumulating data at the application processor until expiration of the application timer. The method comprises sending the accumulated data from the application processor to a modem processor across an interconnectivity bus. The method further comprises holding modem processor data at the modem processor until receipt of the accumulated data from the application processor.

In another aspect, a mobile terminal is disclosed. The mobile terminal comprises a modem timer. The mobile terminal also comprises a modem processor. The modem processor is configured to hold modem processor to application processor data until expiration of the modem timer. The mobile terminal also comprises an application processor. The mobile terminal also comprises an interconnectivity bus communicatively coupling the application processor to the modem processor. The application processor is configured to hold application processor to modem processor data until the modem processor pulls data from the application processor after transmission of the modem processor to application processor data.

With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset. By holding or accumulating the data at a source processor in this fashion, unnecessary transitions between low power states and active states on the PCIe bus are reduced and power is conserved.

In an alternate aspect, instead of initiating data transfer based on the expiration of the downlink timer (with or without expiration of the uplink timer), accumulated data transfer may be initiated based on expiration of just an uplink accumulation timer. The uplink accumulation timer may be within a host or a device associated with the interconnectivity bus.

In another alternate aspect, initiation of the data transfer may be based on reaching a predefined threshold for a byte accumulation limit counter. The byte accumulation limit counter is not mutually exclusive relative to the other counters and may operate as an override mechanism for one of the other accumulation timers. Use of such an override may be useful in situations where a sudden burst of data arrives that would exceed buffer space and/or bus bandwidth. Likewise, instead of a byte counter, a packet size counter or a “total number of packets” counter may be used to cover situations where numerous packets or a particularly a large packet is delivered by the network.

In further aspects of the present disclosure, the timers may be overridden by other factors or parameters. Such an override is alluded to above with the byte accumulation limit counters and the total number of packets counter, which causes data transfers independently of the timers. Other parameters may also override the timers, such as the presence of low latency traffic (e.g., control messages), synchronizing the uplink and downlink data transfers, or low latency quality of service requirements. When such traffic is present, an interrupt or other command may be used to initiate data transfers before expiration of a timer. Still other factors may override the timers, such as an indication that a device or host is not in an automatic polling mode.

While it is contemplated that the power saving techniques of the present disclosure are used in mobile terminals, such as smart phones or tablets, the present disclosure is not so limited. Accordingly,illustrate computing devices coupled to remote networks via modems that may implement exemplary aspects of the power saving techniques of the present disclosure. In this regard,illustrates a computing devicecoupled to a network, which, in an exemplary aspect, is the internet. The computing devicemay include a housingwith a central processing unit (CPU) (not illustrated), therein. A user may interact with the computing devicethrough a user interface formed from input/output elements such as a monitor(sometimes referred to as a display), a keyboard, and/or a mouse. In some aspects, the monitormay be incorporated into the housing. While a keyboardand mouseare illustrated input devices, the monitormay be a touchscreen display, which may supplement or replace the keyboardand mouseas an input device. Other input/output devices may also be present as is well understood in conjunction with desktop or laptop style computing devices. While not illustrated in, the housingmay also include a modem, therein. The modem may be positioned on a network interface card (NIC), as is well understood. Likewise, a router and/or an additional modem may be external to the housing. For example, the computing devicemay couple to the networkthrough a router and a cable modem, as is well understood. However, even where such external routers and modems are present, the computing deviceis likely to have an internal modem to effectuate communication with such external routers and modems.

In addition to the computing device, exemplary aspects of the present disclosure may also be implemented on a mobile terminal, which is a form of computing device as that term is used herein. In this regard, an exemplary aspect of a mobile terminalis illustrated in. The mobile terminalmay be a smart phone, such as a SAMSUNG GALAXY™ or APPLE iPHONE®. Instead of a smart phone, the mobile terminalmay be a cellular telephone, a tablet, a laptop, or other mobile computing device. The mobile terminalmay communicate with a remote antennaassociated with a base station (BS). The BSmay communicate with the public land mobile network (PLMN), the public switched telephone network (PSTN, not shown), or a network(e.g., the internet), similar to the networkin. It is also possible that the PLMNcommunicates with the internet (e.g., the network) either directly or through an intervening network (e.g., the PSTN). It should be appreciated that most contemporary mobile terminalsallow for various types of communication with elements of the network. For example, streaming audio, streaming video, and/or web browsing are all common functions on most contemporary mobile terminals. Such functions are enabled through applications stored in the memory of the mobile terminaland using the wireless transceiver of the mobile terminal.

To effectuate functions, such as streaming video, data arrives from the remote antennaat an antennaof the mobile terminal, as illustrated in. The data is initially processed at a mobile device modem (MDM)of the mobile terminaland passed to an application processorby an interconnectivity bus. In this context, the application processormay be a host, and the MDMmay be a device as those terms are used in the PCIe standard. While exemplary aspects contemplate operating over a PCIe-compliant interconnectivity bus, it is possible that the interconnectivity busmay comply with High Speed Interconnect (HSIC), Universal Asynchronous Receiver/Transmitter (UART), universal serial bus (USB), or the like.

A more detailed depiction of the components of the mobile terminalis provided with reference to. In this regard, a block diagram of some of the elements of the mobile terminalofis illustrated. The mobile terminalmay include a receiver path, a transmitter path, the antenna(mentioned above with reference to), a switch, a modem processor, and the application processor(also introduced above in reference to). Optionally, a separate control system (not shown) may also be present with a CPU as is well understood. The application processorand the modem processorare connected by the interconnectivity bus. The application processorand/or the control system (if present) may interoperate with a user interfaceand memorywith softwarestored therein.

The receiver pathreceives information bearing radio frequency (RF) signals from one or more remote transmitters provided by a base station (e.g., the BSof). A low noise amplifier (not shown) amplifies the signal. A filter (not shown) minimizes broadband interference in the received signal. Down conversion and digitization circuitry (not shown) down converts the filtered, received signal to an intermediate or baseband frequency signal. The baseband frequency signal is then digitized into one or more digital streams. The receiver pathtypically uses one or more mixing frequencies generated by the frequency synthesizer. The modem processormay include a base band processor (BBP) (not shown) that processes the digitized received signal to extract the information or data bits conveyed in the signal. As such, the BBP is typically implemented in one or more digital signal processors (DSPs) within the modem processoror as a separate integrated circuit (IC) as needed or desired.

With continued reference to, on the transmit side, the modem processorreceives digitized data, which may represent voice, data, or control information, from the application processor, which it encodes for transmission. The encoded data is output to the transmitter path, where it is used by a modulator (not shown) to modulate a carrier signal at a desired transmit frequency. An RF power amplifier (not shown) amplifies the modulated carrier signal to a level appropriate for transmission, and delivers the amplified and modulated carrier signal to the antennathrough the switch. Collectively, the modem processor, the receiver path, and the transmitter pathform the MDMof(sometimes also referred to as a wireless modem). While the MDMis specifically described with relation to the RF signals associated with a cellular signal, the present disclosure is not so limited. For example, a wireless modem using other wireless protocols may also benefit from inclusion of aspects of the present disclosure. Thus, modems operating according to standards such as BLUETOOTH®, the various IEEE 802.11 standards, Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Long Term Evolution (LTE), and other wireless protocols may all use aspects of the present disclosure.

With continued reference to, a user may interact with the mobile terminalvia the user interface, such as a microphone, a speaker, a keypad, and a display. Audio information encoded in the received signal is recovered by the BBP, and converted into an analog signal suitable for driving the speaker. The keypad and display enable the user to interact with the mobile terminal. For example, the keypad and display may enable the user to input numbers to be dialed, access address book information, or the like, as well as monitor call progress information. The memorymay have the softwaretherein as noted above, which may effectuate exemplary aspects of the present disclosure.

In conventional mobile terminals that have a PCIe interconnectivity bus (i.e., the interconnectivity bus), the PCIe standard allows the interconnectivity busto be placed into a sleep mode. While placing the interconnectivity busin a sleep mode generally saves power, such sleep modes do have a drawback in that they consume relatively large amounts of power as they transition out of the sleep mode. This power consumption is exacerbated because of the asynchronous nature of the PCIe interconnectivity bus. That is, first data may arrive at the modem processorfor transmission to the application processorat a time different than when the second data is ready to pass from the application processorto the modem processor. This problem is not unique to the PCIe interconnectivity bus.

illustrates a time versus link power graphthat highlights how downlink datamay have a different transmission time than uplink datawithin a given time slot. In particular, the interconnectivity bus() begins in a sleep or low power mode and transitions up to an active power mode by transitionso that the downlink datamay be transmitted to the application processor. However, the downlink datamay not occupy the entirety of the time slot, and the interconnectivity busmay return to a low power state. However, subsequently, but still within the same time slot, the uplink datafrom the application processoris sent to the modem processor. Accordingly, the interconnectivity busis again transitioned from the low power state to the active power state by a second transition. In an exemplary aspect, the time slotis approximately one millisecond long. Thus, if two transitions (i.e.,,) from low power to active power occur every time slot, then thousands of transitions,occur every second. Thousands of transitions,consume substantial amounts of power and reduce the battery life of the mobile terminal.

Exemplary aspects of the present disclosure reduce the number of transitions (i.e.,,) from low power to active power by synchronizing packet transmission from the modem processorand the application processor, which in turn allows the link to be maintained in a low power mode more efficiently since the communication on the link is consolidated to eliminate the second power state transition. In an exemplary aspect, the data (i.e., the modem data) from the modem processortransmits first, and the data (i.e., the application data) from the application processoris sent after arrival of the modem data and before the interconnectivity buscan return to the low power state. The synchronization is done through the use of timers at the modem processorand the application processor. The timers may be longer than a time slotof the interconnectivity bus.

In a first exemplary aspect, the timer on the application processoris longer than the timer on the modem processor. The accumulation may be done on a per logical channel basis. The timer may be configurable by the application processorusing a mechanism suitable to the interconnectivity bus. For example, on a fusion device using a modem host interface (MHI) over PCIe, the timer is maintained for every inbound MHI channel and the time value used by the timers shall be configured via a MHI command message or a PCIe memory mapped input/output (MMIO) device configuration register exposed via a base address register (BAR). The BAR is a PCIe standard defined mechanism by which a host maps the registers of a device into its virtual address map. For more information about MHI, the interested reader is referred to U.S. patent application Ser. No. 14/163,846, filed Jan. 24, 2013, which is herein incorporated by reference in its entirety. In other exemplary aspects, the timer on the modem processoris longer than the timer on the application processor. In still other exemplary aspects, counters may be used in place of timers. The counters may be bit counters, packet counters, packet size counters, or the like. In other exemplary aspects, use of such alternate counters may be combined with the timers. In still other exemplary aspects, other override criteria may allow for data to be sent before timer or counter expiration so as to reduce latency and/or satisfy the quality of service requirements. The present disclosure steps through each of these aspects in turn, beginning with the situation where there are two timers, and the application processorhas a timer that is longer than the timer of the modem processor.

In this regard,illustrates an exemplary power saving process. The processbegins with the interconnectivity busin a low power state (block). The modem timer and the application timer are started (block). The timers may be software stores in the modem processorand the application processoror may be physical elements, as desired. Data is generated by the application processorand data is received from the networkby the modem processor. The application data is held at the application processor(block), and the modem data is held at the modem processor(block) while the timers are running. As noted above, in an exemplary aspect, the time slotof the interconnectivity busis one millisecond. In such an aspect, the modem timer may be approximately two to six milliseconds, and the application timer is three to seven milliseconds, or at least longer than the modem timer. The modem timer expires (block). If modem data is present, the modem data is released by the modem processorthrough the interconnectivity busto the application processor(block).

The mechanism for data transfer may be initiated and controlled by the modem processor(i.e., the device). For example, on a fusion device using MHI over PCIe, the modem processormay poll (read) the MHI channel Context Write Pointer to determine data buffers where downlink packets can be transferred. The application processorupdates the channel context data structure's Context Write Pointer field to point to the data transfer descriptors without ringing an Inbound channel doorbell. The modem processormay poll for updates on the Context Write Pointer field as necessitated by downlink traffic. When the modem processorruns out of buffers, i.e., a transfer ring is empty, and no buffers are present to transfer downlink data, the modem processormay generate an event (e.g., an “out-of-buffer”) notification to the application processor, followed by an interrupt. Upon receiving the event notification from the modem processor, the application processorshall provide data buffers by updating the channel Context Write Pointer and shall ring the Inbound channel doorbell.

After arrival of the modem data at the application processor, the application processorreleases any application data that has been held at the application processorand resets the application timer (block). Note that the application timer can run on the modem processoror the application processor. As an alternative, the modem processormay continue to pull the uplink datafrom the application processoruntil it detects no further downlink dataactivity. That is, the modem processormay intersperse pulling the uplink datawhile receiving the downlink data. If, however, no modem data is present at the modem processorwhen the modem timer expires, the application timer continues (i.e., another millisecond) (block). At the expiration of the application timer, the application processorsends any held data to the modem processorthrough the interconnectivity bus(block). The process then repeats by starting over (block).

As noted above, the uplink timer (i.e., the application timer) is, in an exemplary aspect, designed to be longer than the downlink timer (i.e., the modem timer) to increase the uplink/downlink synchronization whenever the downlink timer expires. While holding data for an extra time slot adds some latency, the brief amount added is readily absorbed by the application processor. Likewise, this latency is considered acceptable for the power savings. For example, by making the period of the modem timer twice the period of the time slot, the number of low power to active power transitions is potentially halved. Likewise, by making the period of the application timer six times the period of the time slot, the chance of being able to “piggyback” onto the active power state of the interconnectivity buscaused by the modem data is increased, but still frequent enough that any uplink datawill still be sent in a timely fashion even if there is no downlink datato trigger releasing the uplink data. Similar logic can be extended to synchronize traffic from multiple processors over the data link. In an exemplary aspect, the other processors may each have timer values higher (i.e., longer) than that of the downlink timer, and the processors can exchange their data availability information so that traffic on one processor can trigger the data transfer on other processors if there is data available to transfer.

illustrates a graphwhere the uplink datafollows the downlink dataduring an active periodof the interconnectivity bus(). As illustrated, there is only one transitionfrom low power to active power per time slot. Thus, by consolidating the data into a single active period, the overall time that is spent in low power may be increased, thus resulting in power savings. Additionally, power spent transitioning from a low power to active power state is reduced by the elimination of the second transition.

While it is conceivable that the uplink datacould be sent before the downlink data(i.e., the application timer is shorter than the modem timer), such is generally not considered optimal because there are usually far more downlink packets than uplink packets. If this aspect is used, the application processormay buffer uplink data packets into local memory prior to initiating transfer to the modem processor. These accumulated packets are controlled via an uplink accumulation timer. If there are plural channels, then a timer may be applied to each channel independently. When the application processoris unable to use or does not have an uplink timer, the modem processormay be able to instantiate an uplink timer, and upon expiry of the uplink timer, will poll data from the application processor. This exemplary aspect is explained in greater detail below with reference to.

In this regard,illustrates an exemplary power saving process. The processbegins with the interconnectivity busin a low power state (block). The modem timer and the application timer are started (block). The timers may be software stored in the modem processorand the application processoror may be physical elements as desired. Data is generated by the application processorand data is received from the networkby the modem processor. The application data is held at the application processor(block), and the modem data is held at the modem processor(block) while the timers are running. As noted above, in an exemplary aspect, the time slotof the interconnectivity busis one millisecond. In such an aspect, the application timer may be approximately two milliseconds, and the modem timer is three milliseconds, or at least longer than the application timer. The application timer expires (block). If application data is present, the application data is released by the application processorthrough the interconnectivity busto the modem processor(block).

After arrival of the application data at the modem processor, the modem processorreleases any modem data that has been held at the modem processorand resets the modem timer (block). Note that the application timer can run on the modem processoror the application processor. Likewise, the modem timer can run on the modem processoror the application processor.

With continued reference to, if no application data is present at the application processorwhen the application timer expires, the modem timer continues (i.e., another millisecond) (block). At the expiration of the modem timer, the modem processorsends any held data to the application processorthrough the interconnectivity bus(block). The process then repeats by starting over (block).

As noted above, in this exemplary aspect, the uplink timer (i.e., the application timer) is, in an exemplary aspect, designed to be shorter than the downlink timer (i.e., the modem timer). While holding data for an extra time slotadds some latency, the brief amount added is readily absorbed by the application processor. Likewise, this latency is considered acceptable for the power savings. For example, by making the period of the application timer twice the period of the time slot, the number of low power to active power transitions is lowered. Likewise, by making the period of the modem timer six times the period of the time slot, the chance of being able to “piggyback” onto the active power state of the interconnectivity buscaused by the application data is increased, but still frequent enough that any downlink datawill still be sent in a timely fashion even if there is no uplink datato trigger releasing the downlink data. Similar logic can be extended to synchronize traffic from multiple processors over the data link. In an exemplary aspect, the other processors may each have timer values higher (i.e., longer) than that of the uplink timer and the processors can exchange their data availability information so that traffic on one processor can trigger the data transfer on other processors if there is data available to transfer.

illustrates a graphwhere the uplink dataprecedes the downlink dataduring an active periodof the interconnectivity bus. As illustrated, there is only one transitionfrom low power to active power per time slot. Thus, by consolidating the data into a single active period, the overall time that is spent in low power may be increased, thus resulting in power savings. Additionally, power spent transitioning from a low power to active power state is reduced by the elimination of the second transition.

In an exemplary aspect, the modem processormay override and choose the minima from all configured values of each of the configurable parameters (like downlink or uplink accumulation timers, byte threshold, number of packets threshold, size of packet threshold, or the like) or downlink accumulation expiry timer values (e.g., from among the various channels) as the effective downlink accumulation timer expiry value. Intelligent modem processorsmay also dynamically override or alter the downlink accumulation timer value depending on the downlink traffic pattern, and/or may adjust the downlink accumulation timer to achieve a desired quality of service (QoS) for data and/or to control traffic. A change of configuration can be triggered/controlled by the application processoror any other processor in the system as well, via MHI control or QMI signaling (such as, for inter process signaling).