Three dimensional semiconductor memory including pillars having joint portions between columnar sections

This application isa reissue of U.S. application Ser. No. 16/936,561 filed Jul. 23, 2020, now U.S. Pat. No. 10,957,710, which isa continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 16/118,567 filed Aug. 31, 2018,now U.S. Pat. No. 10,763,276,and claims the benefit of priority from Japanese Patent Application No. 2017-249588 filed Dec. 26, 2017, the entire contents of each of which are incorporated herein by reference.

Embodiments described herein relate to a semiconductor memory.

A NAND-type flash memory, in which memory cells are three-dimensionally stacked, is known.

A semiconductor memory of the embodiments includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar passing through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion.

Hereinafter, the embodiments will be described with reference to the accompanying drawings. The drawings are schematic views. Each embodiment is an example of an apparatus or a method to embody a technical idea of the invention. In the description below, structural elements having substantially the same functions and configurations will be denoted by the same reference symbols. The numbers after the letters constituting the reference symbols are used to distinguish elements which are denoted by the reference symbols including the same letters and which have similar configurations. If there is no need of mutually distinguishing the elements which are denoted by the reference symbols that include the same letters, the same elements are denoted by the reference symbols that include only the same letters.

A semiconductor memoryaccording to a first embodiment will be described.

[1-1] Configuration

[1-1-1] Configuration of Semiconductor Memory

shows a configuration example of the semiconductor memoryaccording to the first embodiment. The semiconductor memoryis a NAND-type flash memory capable of storing data in a non-volatile manner. As shown in, the semiconductor memoryincludes, for example, a memory cell array, a row decoder, a sense amplifier, and a sequencer.

The memory cell arrayincludes a plurality of blocks BLKO through BLKn (n is an integer equal to or greater than 1). A block BLK is a group of non-volatile memory cells, and is, for example, a data erasure unit. The memory cell arrayincludes a plurality of bit lines and a plurality of word lines, and each memory cell is associated with one bit line and one word line. A detailed configuration of the memory cell arraywill be described later.

The row decoderselects one block BLK based on address information ADD received from an external memory controller. Then, the row decoderapplies each desired voltage to, for example, selected word lines and non-selected word lines.

The sense amplifierapplies each desired voltage to the bit lines on the basis of write data DAT received from the memory controller. The sense amplifieralso determines data stored in a memory cell based on a voltage of a bit line, and transmits determined read data DAT to the memory controller.

The sequencercontrols the operation of the entire semiconductor memorybased on the command CMD received from the memory controller. Communication between the semiconductor memoryand the memory controllersupports, for example, a NAND interface standard. For example, the memory controllertransmits a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn, receives a ready/busy signal RBn, and transmits and receives an input/output signal I/O.

The signal CLE is a signal notifying the semiconductor memorythat the received signal I/O is a command CMD. The signal ALE is a signal notifying the semiconductor memorythat the received signal I/O is address information ADD. The signal WEn is a signal instructing the semiconductor memoryto input the signal I/O. The signal REn is a signal instructing the semiconductor memoryto output the signal I/O. The signal RBn is a signal notifying the memory controllerwhether the semiconductor memoryis in a ready state to receive an instruction from the memory controlleror in a busy state not to receive an instruction from the memory controller. The signal I/O is a signal of, for example, 8 bits, and may include a command CMD, address information ADD, data DAT, etc.

The semiconductor memoryand the memory controlleras described above may be combined to form one semiconductor device. Such a semiconductor device may be a memory card, such as an SD™ card, and an SSD (solid state drive), for example.

[1-1-2] Configuration of Memory Cell Array

(Circuit Configuration of Memory Cell Array)

shows an example of a circuit configuration of the memory cell arrayaccording to the first embodiment, and focuses on one block BLK. The block BLK includes, for example, four string units SU (SUto SU) as shown in.

Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS are respectively associated with bit lines BLthrough BLm (m is an integer equal to or greater than 1). Each NAND string NS includes, for example, memory cell transistors MTthrough MT, dummy transistors LDT and UDT, and select transistors STand ST.

Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the dummy transistors LDT and UDT has a configuration similar to, for example, the configuration of the memory cell transistor MT, and is a memory cell transistor which is not used for storing data. Each of the select transistors STand STis used to select the string unit SU in various operations.

In each NAND string NS, the drain of a select transistor STis coupled to a corresponding bit line BL. The memory cell transistors MTthrough MTare coupled in series between the source of the select transistor STand the drain of the dummy transistor UDT. The source of the dummy transistor UDT is coupled to the drain of the dummy transistor LDT. The memory cell transistors MTthrough MTare coupled in series between the source of the dummy transistor LDT and the drain of the select transistor ST. The source of the select transistor STis coupled to a source line SL.

In one block BLK, the control gates of each of the memory cell transistors MTthrough MTare respectively coupled to word lines WLthrough WLin common. The control gates of the dummy transistors UDT are coupled to a dummy word line UDWL in common. The control gates of the dummy transistors LDT are coupled to a dummy word line LDWL in common. The gates of the select transistors STincluded in each of the string units SUthrough SUare respectively coupled to selection gate lines SGDthrough SGDin common. The gates of the select transistors STare coupled to a selection gate line SGS in common.

Different column addresses, for example, are respectively allocated to the bit lines BLthrough BLm, and each bit line BL couples select transistors STof the NAND strings NS on the same column through the plurality of blocks BLK in common. The word lines WLthrough WLand the dummy word lines UDWL and LDWL, for example, are provided in each block BLK. The source line SL is shared by a plurality of blocks BLK.

In the following description, the plurality of memory cell transistors MT coupled to a common word line WL in one string unit SU are referred to as a “cell unit CU”. The storage capacity of the cell unit CU changes on the basis of the number of bits of data stored in the memory cell transistors MT. For example, the cell unit CU stores one-page data if each of a plurality of memory cell transistors MT in the cell unit CU stores 1-bit data, and the cell unit CU stores two-page data if each of a plurality of memory cell transistors MT in the cell unit CU stores 2-bit data.

(Planar Layout of Memory Cell Array)

shows an example of a planar layout of the memory cell arrayin the first embodiment, an X axis, a Y axis, and a Z axis. Each of the plurality of string units SU extends in the Y direction and is arranged in the X direction, for example, as shown in.

Each string unit SU includes a plurality of memory pillars MH. The plurality of memory pillars MH are, for example, arranged in a staggered manner in the Y direction. At least one bit line BL, for example, is provided to overlap with each memory pillar MH. In each string unit SU, one memory pillar MH is coupled to one bit line BL via a contact plug BLC.

In the memory cell array, a plurality of slits SLT are provided. Each of the plurality of slits SLT, for example, extends in the Y direction and is arranged in the X direction. One string unit SU, for example, is provided between neighboring slits SLT. The number of string units SU provided between neighboring slits SLT is not limited to one, but may be determined as a given number.

(Cross-Section Structure of Memory Cell Array)

shows an example of a cross-section structure of the memory cell arrayin the first embodiment, and shows a cross-section area of the memory cell arrayin which interlayer insulation films are not shown, the X axis, the Y axis, and the Z axis. As shown in, the memory cell arrayincludes a semiconductor substrate, conductorsthrough, the memory pillars MH, and the contact plugs BLC.

The surface of the semiconductor substrateis provided parallel to an XY plane. The conductoris provided above the semiconductor substratewith an insulation film being interposed therebetween. The conductoris formed in a plate-like shape parallel to the XY plane, and functions as, for example, the source line SL. The plurality of slits SLT parallel to a YZ plane are arranged in the X direction on the conductor. The structures above the conductorand between neighboring slits SLT corresponds to, for example, one string unit SU.

For example, a conductor, eight conductors, a conductor, a conductor, eight conductors, and a conductorare provided on the conductorand between neighboring slits SLT in this order from the side of the semiconductor substrate. The conductors adjacent to each other in the Z direction among these conductors are stacked with an interlayer insulation film being interposed therebetween. Each of the conductorsthroughis formed in a plate-like shape parallel to the XY plane.

For example, the conductorfunctions as the selection gate line SGS. The eight conductorsrespectively function as the word lines WLto WLin the order from the bottom. The conductorsandrespectively function as the dummy word lines LDWL and UDWL. The eight conductorsrespectively function as the word lines WLto WLin the order from the bottom. The conductorfunctions as a selection gate line SGD.

Each of the plurality of memory pillars MH functions as, for example, one NAND string NS. Each memory pillar MH is provided to pass through the conductorsthroughin a manner that each memory pillar MH extends from the upper surface of the conductorto reach the upper surface of the conductor. Furthermore, each memory pillar MH is formed by connecting a plurality of columnar sections, and includes, for example, a lower pillar LMH, an upper pillar UMH, and a joint portion JT between the lower pillar LMH and the upper pillar UMH. The upper pillar UMH is provided above the lower pillar LMH, and the lower pillar LMH and the upper pillar UMH are joined to the joint portion JT interposed therebetween.

In addition, the memory pillar MH includes, for example, a block insulation film, an insulation film, a tunnel oxide film, and a conductive semiconductor material. The block insulation filmis provided on the inner wall of a memory hole forming the memory pillar MH. The insulation filmis provided on the inner wall of the block insulation film, and functions as a charge storage layer of the memory cell transistor MT. The tunnel oxide filmis provided on the inner wall of the insulation film. The semiconductor materialis provided on the inner wall of the tunnel oxide film, and a current pathway of the NAND string NS is formed in the semiconductor material. The memory pillar MH may include a different material inside the conductive semiconductor material.

The part where the memory pillar MH crosses the conductorfunctions as the select transistor ST. The parts where the memory pillar MH crosses the eight conductorsrespectively function as the memory cell transistors MTthrough MTin this order from the bottom. The part where the memory pillar MH crosses the conductorfunctions as the dummy transistor LDT. As shown in the drawing, the select transistor ST, the memory cell transistors MTthrough MT, and the dummy transistor LDT are each formed by the lower pillar LMH.

The part where the memory pillar MH crosses the conductorfunctions as the dummy transistor UDT. The parts where the memory pillar MH crosses the eight conductorsrespectively function as the memory cell transistors MTthrough MTin this order from the bottom. The part where the memory pillar MH crosses the conductorfunctions as the select transistor ST. As shown in the drawing, the dummy transistor UDT, the memory cell transistors MTthrough MT, and the select transistor STare each formed by the upper pillar UMH.

shows an example of a detailed cross-section structure of the memory cell array, focusing on an area including the joint portion JT. As shown in, an outer diameter JDI of the joint portion JT in a cross-section area parallel to the XY plane is larger than an outer diameter LDI of the lower pillar LMH in a cross-section area parallel to an XY plane which includes a boundary portion between the lower pillar LMH and the joint portion JT, and is larger than an outer diameter UDI of the upper pillar UMH in a cross-section area parallel to the XY plane which includes a boundary portion between the upper pillar UMH and the joint portion JT. The term “outer diameter” in this specification indicates the outer diameter of the block insulation filmin the memory pillar MH.

For example, the conductor(the dummy word line LDWL), through which the lower pillar LMH passes and that is provided next to the joint portion JT, does not have a portion bending along the joint portion JT. On the other hand, the conductor(the dummy word line UDWL), through which the upper pillar UMH passes and that is provided next to the joint portion JT, has a portion BEbending along the shape of the joint portion JT.

The conductor(the word line WL), through which the upper pillar UMH passes and that is provided next to the conductor, has a portion BEbending indirectly along the shape of the joint portion JT. In other words, the conductorbends along the portion where the conductorbends along the joint portion JT. In this case, a bending amount of the conductor(the dummy word line UDWL) at the portion BEis larger than a bending amount of the conductor(the word line WL) at the portion BE.

The portion where the conductorbends along the joint portion JT and directly or indirectly comes into contact with the joint portion JT is hereinafter called a bending portion ST. At the bending portion ST, an insulation film different from the block insulation filmmay be provided between the joint portion JT and the conductor.

The bending portion ST is formed by a diameter difference between the outer diameter UDI and the outer diameter JDI. A height ΔST indicates the size of the bending portion ST in the Z direction. Specifically, the height ΔST is defined by, for example, the distance in the Z direction between a cross-section area, which is parallel to the XY plane and includes a portion of the bending portion ST which is the most distant from the semiconductor substratein the Z direction, and a cross-section area, which is parallel to the XY plane and includes a portion of the bending portion ST which is the closest to the semiconductor substratein the Z direction.

Furthermore, the height ΔST is determined to be, for example, smaller than a thickness LTS of the conductorin the Z direction, and is preferably determined to be equal to or smaller than a half of the thickness LTS. The thickness LTS of the conductoris preferably measured by using an area of the conductorwhich does not include the bending portion ST.

A distance JTS in the Z direction between the conductorsandis determined to be, for example, larger than the distance between adjacent conductorsin the Z direction, and larger than the distance between adjacent conductorsin the Z direction.

For example, the plurality of memory pillars MH include a first pillar and a second pillar adjacent to each other.

A distance in the Z direction between the semiconductor substrateand an upper end of the conductorat a position between the first and second pillars is smaller than a distance in the Z direction between the semiconductor substrateand an upper end of a portion where the conductorcomes into contact with the first pillar.

A distance in the Z direction between the semiconductor substrateand an upper end of the conductorat a position between the first and second pillars is approximately equal to a distance in the Z direction between the semiconductor substrateand an upper end of a portion where the conductorcomes into contact with the first pillar.

a distance in the Z direction between the semiconductor substrateand an upper end of a conductordistant from the conductorat a position between the first and second pillars is approximately equal to a distance in the Z direction between the semiconductor substrateand an upper end of a portion where said conductorcomes into contact with the first pillar.

Referring back to, the conductoris provided above the upper surface of the memory pillar MH with an interlayer insulation film interposed there between. The conductoris formed in a linear shape extending in the X direction, and functions as the bit line BL. A plurality of conductorsare arranged in the Y direction (not shown), and each conductoris electrically coupled to one corresponding memory pillar MH in each string unit SU.

Specifically, in each string unit SU, for example, the conductive contact plug BLC is provided on the semiconductor materialin each memory pillar MH, and one conductoris provided on the contact plug BLC. The memory pillar MH and the conductormay be coupled via a plurality of contact plugs, wires, etc.