Memory arrays

The patent resulted from aprovisional applicationreissue continuation of U.S. Reissue patent application Ser. No. 17/463,420, filed Aug. 31, 2021, now RE49,715, which is a reissue application of U.S. Pat. No. 10,607,995, issued Mar. 31, 2020, which resulted from U.S. patent application Ser. No. 15/973,697, filed May 8, 2018, which claims the benefitof U.S.ProvisionalPatent Application Ser. No. 62/502,999, filed May 8, 2017, entitled “Memory Arrays”, naming Martin C. Roberts, Sanh D. Tang and Fred D. Fishburn as inventors, the disclosures of which are incorporated by reference.

Embodiments disclosed herein pertain to memory arrays.

Memory is one type of integrated circuitry, and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line.

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates, and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiOwill be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Programmable materials other than ferroelectric materials may be used as a capacitor insulator to render capacitors non-volatile.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example reversibly programmable charge storage/trap regions as part of the gate construction between the gate insulator and the conductive gate.

One type of transistor is a ferroelectric field effect transistor (FeFET) wherein at least some portion of the gate construction (e.g., the gate insulator) comprises ferroelectric material. The two different polarized states of the ferroelectric material in field effect transistors may be characterized by different threshold voltage (V) for the transistor or by different channel conductivity for a selected operating voltage. Again, polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and which results in one of high channel conductance or low channel conductance. The high and low conductance, invoked by the ferroelectric polarization state, remains after removal of the gate programming voltage (at least for a time). The status of the channel can be read by applying a small drain voltage which does not disturb the ferroelectric polarization. Programmable materials other than ferroelectric materials may be used as a gate insulator to render a transistor to be non-volatile.

Embodiments of the invention encompass memory arrays. A first example embodiment is shown in and described with references to. Such includes a substrate structure or constructioncomprising a memory arrayfabricated relative to a base substrate. Substratemay comprise any one or more of conductive/conductor/conducting (i.e., electrically herein), semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate. Materials may be aside, elevationally inward, or elevationally outward of the-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate. Control and/or other peripheral circuitry for operating components within a memory array may also be fabricated, and may or may not be wholly or partially within a memory array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

Constructionincludes vertically-alternating tiersandof insulative material(e.g., comprising, consisting essentially of, or consisting of carbon-doped silicon nitride [2 to 10 atomic percent carbon], silicon nitride, and/or doped or undoped silicon dioxide deposited to a thickness of 200 Angstroms to 500 Angstroms) and memory cells, respectively. Only three memory cell outlinesare shown infor clarity, although three complete and three partial memory cells are visible in. Analogously, only six memory cell outlinesare shown in, although more memory cells are visible in. Memory cell tiersmay be of the same or different thickness as that of insulative material tiers, with different and greater thickness being shown (e.g., 500 Angstroms to 2,000 Angstroms). Constructionis shown as having seven vertically-alternating tiersand, although fewer or likely many more (e.g., dozens, hundreds, etc.) may be formed. Accordingly, more tiersandmay be below the depicted tiers and above base substrateand/or more tiersandmay be above the depicted tiers.

Memory cellsindividually comprise a transistorand a capacitor. Transistorcomprises a first source/drain regionand a second source/drain region(e.g., conductively-doped semiconductor material such as polysilicon for each) having a channel regionthere-between (e.g., doped semiconductor material, such as polysilicon, but not to be intrinsically conductive). In some embodiments (but not shown), a conductively-doped semiconductor region and/or or an electrically semiconductive region (e.g., LDD and/or halo regions) may be between channel regionand one or both of source/drain regionsand.

A gateor(e.g., one or more of elemental metal, a mixture or alloy of two or more elementals, conductive metal compounds, and conductively-doped semiconductive materials) is operatively proximate channel region. Specifically, in the depicted example, a gate insulator material(e.g., silicon dioxide, silicon nitride, hafnium oxide, other high k insulator material, and/or ferroelectric material) is between gate/and channel region. In one embodiment and as shown, individual memory cell tierscomprise gateand another gate, with one of such gates (e.g., gate) being directly above the other (e.g., gate) in that individual memory cell tier. At least a portion of channel regionis horizontally-oriented for horizontal current flow in the portion between first source/drain regionand second source/drain region. In the depicted example embodiment, all of channel regionis horizontally-oriented for horizontal current flow there-through. Regardless, when suitable voltage is applied to gateand/or, a conductive channel can form within channel regionproximate gate insulator materialsuch that current is capable of flowing between source/drain regionsand.

In one embodiment and as shown, channel regioncomprises an annulusin a straight-line horizontal cross-section (e.g., the cross-section shown by). In one embodiment and as shown, gatecomprises an annulusin a straight-line horizontal cross-section. (e.g., the cross-section shown by). In one embodiment and as shown, first source/drain regioncomprises an annulusin a straight-line horizontal cross-section (e.g., the cross-section shown by). In one embodiment and as shown, second source/drain regioncomprises an annulusin a straight-line horizontal cross-section (e.g., the cross-section shown by).

One or both of gatesandmay be part of an access line (e.g., two access linesx andy being shown) interconnecting multiple transistors along a row or a column. Regardless, in one embodiment that includes both of gatesand, such gates are directly electrically coupled to one. As examples, and by way of examples only, one or more staircase regions(one being shown in) may be provided at an end of or as a part of array. Staircase regionas shown comprises staggered contact openingsindividually having a conductive via(e.g., metal material) therein that directly electrically couples together vertically-stacked gatesandin individual memory cell tiers. Conductive viasmay connect with a respective conductive control and/or access line (not shown) to separately access gate line pairs,in each memory cell tier.

Capacitorcomprises a first electrodeand a second electrode(e.g., conductively-doped semiconductive material and/or metal material for each) having a capacitor insulatorthere-between (e.g., silicon dioxide, silicon nitride, hafnium oxide, other high k insulator material, and/or ferroelectric material). Second capacitor electrode materialand capacitor insulatorare not separately distinguishable indue to scale. First electrodeis electrically coupled, in one embodiment directly electrically coupled, to first source/drain region. Second electrodesof multiple of capacitorsin arrayare electrically coupled, in one embodiment are directly electrically coupled, with one another. In one embodiment, all such second electrodes of all capacitors in arrayare electrically coupled with one another, and in one embodiment are directly electrically coupled with one another. In one embodiment and as shown, second electrodeis both directly above and directly below first electrodein a straight-line vertical cross-section (e.g., the cross-section depicted by). In one embodiment and as shown, first electrodecomprises an annulusin a straight-line horizontal cross-section (e.g., the cross-section shown by), and in one embodiment second electrodecomprises an annulusin a straight-line horizontal cross-section (e.g., the cross-section shown by). In one embodiment and as shown, one gateor(e.g.,) extends longitudinally directly above capacitorin a straight-line vertical cross-section (e.g., the cross-section shown by), and in one embodiment other gateor(e.g.,) extends longitudinally directly under capacitorin a straight-line vertical cross-section (e.g., the cross-section shown by).

In one embodiment, a capacitor-electrode structure(e.g., a solid or hollow pillar, a solid or hollow wall, etc.) extends elevationally through vertically-alternating tiersand, with individual of second electrodesof individual capacitorsthat are in different memory cell tiersbeing electrically coupled, in one embodiment directly electrically coupled, to elevationally-extending capacitor-electrode structure. Example materials for capacitor-electrode structureare metal materials and conductively-doped semiconductor material. In one embodiment and as shown, capacitor-electrode structureextends vertically or within 10° of vertical. In one embodiment and as shown, capacitor-electrode structurecomprises an elevationally-extending wallthat is longitudinally-elongated horizontally and that directly electrically couples the individual second capacitor together. In one embodiment, such, by way of example only, is one example of how second capacitor electrodesof multiple of capacitorsthat are in different memory cell tiersin the array may be electrically coupled with one another. In one embodiment, capacitor-electrode structureis directly electrically coupled to a horizontally-elongated capacitor-electrode construction(e.g., a line or a plate) that is above or below (above being shown) vertically-alternating tiersand. Construction(s)may, in one embodiment, directly electrically couple together all second electrodeswithin the array.

A sense line is electrically coupled, in one embodiment directly electrically coupled, to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers. In one embodiment and as shown, a sense-line structure(e.g., a solid or hollow pillar, a solid or hollow wall, etc.) extends elevationally through vertically-alternating tiersand, with individual of second source/drain regionsof individual transistorsthat are in different memory cell tiersbeing electrically coupled, in one embodiment directly electrically coupled, thereto. In one embodiment and as shown, sense-line structureextends vertically or within 10° of vertical. In one embodiment and as shown, sense-line structurecomprises a pillar. In one embodiment and as shown, sense-line structurecomprises a peripheral conductively-doped semiconductive material(e.g., poly silicon) and a central metal material core(e.g., titanium nitride and/or tungsten). In one embodiment, sense-line structureis directly electrically coupled to a horizontal longitudinally-elongated sense linethat is above or below (below being shown) vertically-alternating tiersand.

Example insulator material(e.g., silicon nitride) and insulator material(e.g., silicon dioxide) may be provided as shown for suitable isolation in sub-tiers of memory cell tiers.

An alternate embodiment constructiona of a memory arrayis shown in. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”. Only one tiera and two tiersare shown for clarity. The channel region of transistora comprises two channel-region segmentsa that are spaced elevationally apart from one another in a straight-line vertical cross-section (e.g., the cross-section shown by). In one such embodiment, such two channel-region segmentsa are directly electrically coupled to one another, and in one such embodiment as shown are so coupled by first source/drain regiona. In one embodiment and as shown, second electrodea of capacitora is not both directly above and directly below first electrodea in any straight-line vertical cross-section. In one embodiment and as shown, first electrodea is both directly above and directly below second electrodea in a straight-line vertical cross-section (e.g., the cross-section shown by). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

shows another example alternate embodiment constructionb of a memory array, with individual memory cells comprising a transistorb and a capacitorb. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b”. Again, only one tierb and two tiersare shown. Transistorb comprises only a single gate(e.g., no additional gate) associated with channel region. Such is shown as being above channel region, although such may alternately be there-below. Accordingly, capacitorb may be considered as being single-sided whereas capacitorsanda may be considered as being at least double-sided (e.g., top and bottom sided with respect to capacitor electrode,a). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, individual of the memory cell tiers have no two of the memory cells that are directly above and directly below one another in that individual memory cell tier. For example, and by way of example only, the above described embodiments with respect toshow such example embodiments. Alternately, and by way of example only, individual of the memory cell tiers may comprise two of the memory cells where one of which is directly above the other in that individual tier of memory cells. A first example such embodiment is shown and described with respect toand a constructionc of a memory array. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “c”. Again, only one tierc and two tiersare shown.

Individual memory cellsin a single tierc are shown as comprising a transistorc and a capacitorc. One of memory cellsis above another memory cellin an individual tierc as shown in the example embodiment. In one embodiment as shown, each capacitorc shares a capacitor electrodec that extends to or is part of capacitor-electrode structure. Second source/drain regionsof the depicted different transistorsc may be electrically coupled, in one embodiment directly electrically coupled, to one another for example as shown by conductive materialsandas part of sense-line structure. First source/drain regionsof each transistorc are not directly electrically coupled to one another, and are electrically coupled, in one embodiment directly electrically coupled, with respective first capacitor electrodesc. Thereby, two vertically-stacked memory cells(one directly above the other) are formed within a single memory cell tierc. Transistor gatesand, in one embodiment, are not directly electrically coupled to one another which may enable better separate access/control with respect to different transistorsc that are above and below one another within an individual memory cell tierc. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

A second example such embodiment is shown and described with respect toand a constructiond of a memory array. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “d”. Again, only one tierd and two tiersare shown. Example constructiond is very similar to constructionc, with each memory cellhaving a transistord and capacitorc. Transistord differs from transistorc in having second source/drain regionsd that integrally connect with one another elevationally along and aside sense-line structure. Still, individual memory cell tiersd comprise two of memory cellswhere one of such is directly above the other in that individual tier of memory cells.

In one embodiment that includes both of gatesand, such gates are not directly coupled to one another. For example, such an embodiment is shown and described with respect toand a constructione of a memory array. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “e”. Staircase regione comprises staggered contact openingse individually having a conductive viae therein that separately extend to different individual gatesandin individual memory cell tiers, thereby not directly coupling together gatesandin individual memory cell tiers.

The above example structures may be manufactured by any existing or yet-to-be-developed techniques. One example technique of manufacturing the embodiment shown byis described with reference to. Like numerals from the above-described embodiments have been used for predecessor construction(s), regions, and like/predecessor materials thereof.

show an example portion of a predecessor to the construction or stack of. The person of skill in the art may select any suitable different combinations of materials recognizing, in accordance with the continuing description, that certain materials will be etched selectively relative to other materials in the example method. As examples, and consistent with those described above, example materialfor insulative-material tiersis carbon-doped silicon nitride (2 to 10 atomic percent carbon). An example thickness for insulative materialis 200 to 500 Angstroms. Constructionincludes a stack of materials or layers,,,, and(top-to-bottom), and each of which may be considered as a sub-tier within what will be memory cell tiers. Example thickness for each of materials,, andis 100 to 400 Angstroms, with example gate materialsandbeing n+ conductively-doped polysilicon. An example insulator materialis silicon nitride. Materialsand/ormay be sacrificial and replaced by conductively-doped semiconductive material and/or metal material. An example insulator materialis silicon dioxide, with an example thickness being 300 to 600 Angstroms. Constructionhas been patterned to form staircase regionwhereby individual gate materialsandin individual memory cell tiersform uppermost surfaces of so-called “stairs” that may subsequently be upwardly-exposed as will become apparent from the continuing discussion. Example silicon-dioxide-insulator materialis atop the stairs in staircase region.

Referring to, openingshave been formed in and through the depicted stack of materials in an offset or staggered manner. The centers of example openingsare centered relative to what will be the centers of sense-line structures(not shown) and annuli,,, and(not shown).

Referring to, substrate constructionofhas been subjected to suitable etching whereby materialhas been etched laterally/radially selectively relative to the other depicted materials effective to widen openingswithin memory cell tiers. With respect to the above example materials, an example etching chemistry is dilute HF. An example uppermost silicon nitride insulator layerprotects example silicon-dioxide-insulator materialthere-under from being etched in staircase region.

Referring to, second capacitor electrode material(e.g., titanium nitride at 30 to 60 Angstroms), capacitor insulator/gate insulator(e.g., silicon dioxide and/or a high k insulator at 30 to 60 Angstroms), and first capacitor electrode material-first source/drain material(e.g., conductively-dope polysilicon at 50 to 100 Angstroms) have been deposited as shown. Second capacitor electrode materialand capacitor insulator/gate insulatorare not separately distinguishable in, nor in subsequent corresponding odd-numbered figures, due to scale. Insulator material/may be silicon dioxide that is subjected to in situ steam generation immediately after its deposition for densification (e.g., at 650° C. to 1000° C., atmospheric or sub-atmospheric pressure, and in the presence of Oand H). Material/has been deposited sufficient to fill the laterally-widened portions of openings, but ideally not sufficient to fill the central portion of the narrower part of such openings.

Referring to, material/has been etched as shown to form finished first capacitor electrodeand first source/drain region(and corresponding annuliand, respectively). An example etching chemistry to conduct the example depicted selective etch for the stated materials is tetra-methylammonium hydroxide (TMAH).

Referring to, intrinsic or suitably-doped channel-material siliconhas been deposited and subsequently etched back as-shown to set the channel length (e.g., 200 Angstroms) and define channel annuli. An example etching chemistry for the stated materials is TMAH.

Referring to, more silicon-oxide-insulator materialhas been deposited effective to fill the depicted recesses/gaps that were formed by the etching of channel materialshown in in, followed by selective etch thereof (e.g., dilute HF) to remove such form the main portion of openings.

Referring to, insulator material/has been etched, followed by etching of titanium nitride second capacitor electrode material, to remove such from being within the main portion of openings. Example etching chemistries include, respectively, dilute HF and a combination of hydrogen peroxide and sulfuric acid. Thereafter, example silicon nitride insulator materialhas been suitably etched (e.g., using hot phosphoric acid) to remove the uppermost layerand to laterally recess materialwithin memory cell tiersas shown. Such also thereby exposes elevationally uppermost and elevationally lowermost surfaces of second capacitor electrode materialwhere silicon nitride insulator materialhas been removed in memory cell tiers.

Referring to, example titanium nitride materialhas been subjected to selective etching (e.g., using sulfuric acid and hydrogen peroxide) sufficient to recess it laterally/radially as shown and to form elevational gaps/recesses between insulator material/and example silicon nitrideat radially inner ends (relative to openings) of silicon nitride.

Referring to, insulator materialhas been formed within the elevational gaps/recesses that were formed by the etching shown in. An example technique for producing theconstruction is a conformal deposition of example silicon-dioxide-insulator material, followed by etch back (e.g., using dilute HF) to remove such except where received in the depicted gaps/recesses.

Referring to, more example n+ conductively-doped polysilicon gate material,has been deposited to fill the remaining gaps/recesses shown in, followed by selective etching of material,(e.g., using TMAH) to laterally recess it as shown.

Referring to, example silicon-nitride-insulator materialhas been deposited to fill the gaps that were formed by the etching shown in, followed by selective etch thereof (e.g., using hot phosphoric acid) to remove such from being within the main portion of openings.

Referring to, example silicon-dioxide-insulator materialthat was formed as described above with respect to(not shown in) has been removed by selective etching (e.g., HF). Suring such etching, some silicon-dioxide-insulator materialin staircase regionmay also be etched (not shown). Alternately, uppermost silicon-nitride insulator material(not shown) shown inmay initially be sufficiently thick such that all of it is not removed in the processing shown bysuch that some of it remains (not shown) and protects staircase-region-silicon-oxide materialduring removal of materialthat was formed as shown in.

Referring to, second source/drain region material/materialhas been deposited as shown sufficient to fill the gaps formed by removing materialas shown in. Subsequently, metal materialhas been deposited and planarized and/or etched back as-shown to form sense-line structures. Uppermost portions of materialsandhave been removed as shown and openings formed thereby have been plugged with insulator material.

Referring to, a trenchhas been formed (e.g., using lithography and subtractive etch with or without pitch multiplication) as shown. Such effectively enables longitudinal outlines of access linesx andy (not shown yet) to be formed, as well as formation of capacitor-electrode structures(not shown yet) as will be apparent from the continuing discussion.

Referring to, example polysilicon material,has been selectively etched as-shown (e.g., using TMAH), thereby forming the longitudinal outlines of access linesx andy.

Referring to, example silicon-nitride-insulator materialhas been used to plug the gaps/recesses formed by the etching shown in, and then such materialhas been removed from the main portion of trenches.

Referring to, example silicon-dioxide-insulator materialhas been etched selectively (e.g., using HF) laterally sufficient to expose ends of second capacitor electrode materialas shown.

Referring to, additional second capacitor electrode materialhas been deposited to fill trenchesand the gaps/recesses formed by the etching shown in, thus completing formation of capacitor-electrode structures. Horizontally-elongated capacitor-electrode constructionmay fabricated at this time (e.g., by subtractive patterning of materialof capacitor-electrode structures).

Referring to, contact openingshave been formed in staircase regionto upwardly expose and overlap with conductive gate materialandwithin individual memory cell tiers.

Referring to, contact openingshave been filled with conductive material which has then been planarized back to form conductive vias.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors that are in different memory cell tiers are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to multiple of the second source/drain regions of individual of the transistors.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors that are in different memory cell tiers are electrically coupled to the elevationally-extending capacitor-electrode structure.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense line is electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers. Individual of the tiers of memory cells comprise two of the memory cells one of which is directly above the other in that individual tier of memory cells.

In some embodiments, a memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense line is electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers. Individual of the tiers of memory cells comprise the gate and another gate. One of the gate and the another gate is directly above the other in that individual tier of memory cells.