Memory module, error correction method of memory controller controlling the same, and computing system including the same

This U.S. non-provisional patent application claims benefit of priority under 35 USC 119(a) to Korean Patent Application No. 10-2019-0116041 filed on Sep. 20, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

The present disclosure relates to a memory module, an error correction method of a memory controller controlling the memory module, and a computing system including the memory module.

Data may be stored in a memory of a memory system along with an error correction code (ECC). If the data later develops one or more errors, the corresponding ECC can be used to potentially correct the errors. Examples of the ECC include block codes and convolution codes.

A memory controller or other logic of the memory system may perform error detection on the data and correction of the data using one or more ECCs. The logic being located within a die may be referred to as an on-die ECC circuit. Common memory architectures for the on-die ECC circuit include a 4-bit wide interface (i.e., x4 interface), an 8-bit wide interface (i.e., x8 interface), or a 16-bit wide interface (i.e., x16 interface). The design and number of required ECC bits for implementing ECC are mainly dictated by the memory architecture.

Exemplary embodiments of the inventive concept provide a memory module configured to improve error correction ability while preventing deteriorations in performance, an error correction method of a memory controller configured to control the memory module, and a computing system including the memory module.

According to an exemplary embodiment of the inventive concept, a memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

According to an exemplary embodiment of the inventive concept, a memory module includes a first sub-channel, a second sub-channel, and a driver circuit configured to receive a clock signal, first and second commands, and an address from a memory controller and to transmit the clock signal, the first command, and the address to the first sub-channel and transmit the clock, the second command, and the address to the second sub-channel. Each of the first and second sub-channels includes first memory chips, each having a first input/output width and configured to store data, and a second memory chip having a second input/output width, less than the first input/output width, and configured to store an error correction code for correcting an error in the data. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

According to an exemplary embodiment of the inventive concept, an error correction method of a memory controller is provided. The memory controller is configured to control a memory module including first memory chips, each having a first input/output width, and configured to store data and at least one second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data. The error correction method includes: determining whether the data, received from the memory module, includes an error that is correctable; determining whether physical replacement of a memory cell storing the data is required; selecting a first error correction mode when the error is correctable and the physical replacement is required; selecting a second error correction mode when the error is correctable and the physical replacement is not required; and performing an error correction operation on the data according to the selected mode.

According to an exemplary embodiment of the inventive concept, a computing system is provided that includes at least one memory module, at least one nonvolatile memory module, and at least one processor configured to control the at least one memory module and the at least one nonvolatile memory module. The at least one memory module includes at least one first memory chip, having a first input/output width and configured to store data, and at least one second memory chip having a second input/output width, different from the first input/output width, and configured to store an error correction code for correcting an error in the data.

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

A memory system according to an exemplary embodiment of the inventive concept includes a memory module including a first memory chip and a second memory chip having input and output widths that differ from each other. The first memory chip and the second memory chip may have separate address controls to extend an error correction code (ECC) range without causing deteriorations in performance.

illustrates a memory systemaccording to an exemplary embodiment of the inventive concept. Referring to, the memory systemmay include a memory moduleand a memory controller.

The memory modulemay temporarily store data processed or to be processed by a processor. The memory modulemay be used as an operating memory, a working memory, or a buffer memory in a computing system. The memory moduleincludes first memory chips, at least one second memory chip, and a registered clock driver (RCD)(e.g., a driving circuit).

In an exemplary embodiment, the memory modulemay be implemented as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small-outline DIMM (SODIMM), an unbuffered DIMM (UDDIMM), a Fully-Buffered DIMM (FBDIMM), a Rank-Buffered DIMM (RBDIMM), a mini-DIMM, a micro-DIMM, a Registered DIMM (RDIMM), or a Load-Reduced DIMM (RDIMM).

Each of the first memory chipsmay be implemented to store data transmitted from the memory controller. In exemplary embodiment, each of the first memory chipsmay be a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a low power double data rate SDRAM (LPDDR SDRAM), a graphics double data rate SDRAM (GDDR SDRAM), a Rambus DRAM (RDRAM), or a static RAM (SRAM). In another embodiment, each of the first memory chipsmay be a nonvolatile memory such as a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), or a flash memory. In an exemplary embodiment, each of the first memory chipsmay be implemented as a DRAM chip according to various standards such as Double Data Rate (DDR), DDR2, DDR3, DDR4, and DDR5. In an exemplary embodiment, each of the first memory chipsis implemented to input and output data through n data channels DQ [1:n], where n is a positive integer greater than or equal to 2.

The second memory chipmay be implemented to store parity (e.g., parity data) for correcting an error of data stored in the first memory chips. In an exemplary embodiment, the second memory chipmay be a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, or SRAM. In another exemplary embodiment, the second memory chipmay be a nonvolatile memory such as PRAM, MRAM, ReRAM, FRAM, or flash memory. In an exemplary embodiment, the second memory chipmay be implemented as a DRAM chip according to various standards such as DDR, DDR2, DDR3, DDR4, and DDR5. In an exemplary embodiment, the second memory chipis implemented to input and output data through m data channels DQ [1: m], where m is a positive integer less than n.

In an exemplary embodiment, a storage capacity of each of the first memory chipsand a storage capacity of the second memory chipare equal to each other.

The registered clock driver (RDC)may be implemented to receive a command CMD, an address ADD, and a clock signal CK from the memory controller. The RCDmay transmit the received command CMD, the received address ADD, and the received clock signal CK to the first memory chipsand the second memory chip.

Although not illustrated in, the memory modulemay further include a serial presence detect (SPD) chip. The SPD chip may be implemented to store information on characteristics of the memory module. In an exemplary embodiment, the SPD chip may store memory module information such as a module type, an operating environment, a line arrangement, a module configuration, and a storage capacity of the memory module. In an exemplary embodiment, the SPD chip may include a programmable read-only memory such as an electrically erasable programmable read-only memory (EEPROM).

The memory controllermay be implemented to transmit and receive a command/address CMD/ADD, a clock signal CK, a control signal, data DQ, and a data strobe signal DQS to and from the memory modulethrough a channel. In an exemplary embodiment, the memory controllercontrols reading of the data DQ from the memory moduleand writing of the data DQ into the memory module. In an exemplary embodiment, the memory controllerprovides the command/address CMD/ADD and the control signal to the memory module, and may control transmitting and receiving of the data DQ to and from a memory chip to be accessed, among the memory chips, based on the control signal in a writing or reading operation corresponding to the command/address CMD/ADD. For example, the writing operation may performed in response to a CMD of a writing command and the reading operation may be performed in response to a CMD of a reading command.

In an exemplary embodiment, the memory controlleris connected to an external host such as a processor. For example, the memory controllermay communicate with the external host through at least one of various interface protocols such as Universal Serial Bus (USB), MultiMediaCard (MMC), Parallel Connection Interface (PCI), Parallel Connection Interface Express (PCIe), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Device Interface (ESDI), or Integrated Drive Electronics (IDE).

In an exemplary embodiment, the memory controllermay be configured as an additional chip or may be integrated with the memory module. For example, the memory controllermay be implemented on a motherboard and may be implemented as an integrated memory controller (IMC) included in a microprocessor. In addition, the memory controllermay be disposed in an input/output hub, and the input/output hub including the memory controllermay be referred to as a memory controller hub (MCH).

The memory controllerincludes an ECC engine(e.g., a circuit) to perform error detection and correction operations.

The ECC enginemay use at least one of a Parity-Check, Cyclical Redundancy Code Check (CRC Check), Checksum Check, and Hamming Code to detect errors and correct the detected errors. In an exemplary embodiment, the ECC enginemay use a correction scheme such as x4 Single Device Data Correction (SDDC), x8 Single-bit Error Correction and Double-bit Error Detection (SECDED), or Lockstep x8 SDDC to correct errors of a plurality of memory chips.

In an exemplary embodiment, the ECC engineoperates in one of a first error correction mode and a second error correction mode. The first error correction mode is a soft error correction mode, and the second error correction mode is a hard error correction mode. In the soft error correction mode, data of the first memory chipsis corrected using m parities of the second memory chip. In the hard error correction mode, data of the first memory chipsis corrected using 2 m parities of the second memory chip.

In an exemplary embodiment, the ECC enginedetermines whether error correction is possible for data of the first memory chipsin the first error correction mode, and performs a soft error correction operation when the error correction is determined to be possible (e.g., when an error is determined to be correctable). In an exemplary embodiment, the ECC engineperforms a hard error correction operation on the data of the first memory chipsin the second error correction mode when an error is correctable but physical replacement (redundancy cell replacement) is required. For example, if the data is stored in an original memory cell that has been determined to be unreliable, after the data is corrected, it can be stored in the redundancy cell. In an exemplary embodiment, a mapping table that maps a logical address to a physical address of the original memory cell is updated to map the logical address to a physical address of the redundancy memory cell.

In an exemplary embodiment, the ECC enginereads a parity from the second memory chipdepending on an error correction mode selected using at least one address of an ECC-only second memory chip. The at least one address may be a row address, a column address, a bank address, or a bank group address.

A common memory system includes memory chips, having the same input and output width, to operate within an ECC error correction range limited by a memory module. On the other hand, the memory systemaccording to an exemplary embodiment of the inventive concept separates address controls of the first memory chipsand the second memory chipin a memory module, in which the first memory chipsstoring data and the second memory chipstoring a parity of the data are configured to have different input/output widths from each other, to extend an ECC error correction range width depending on a predetermined scheme.

illustrate common memory modules, each including memory chips having the same input/output width. Referring to, each of sub-channels A and B may input and output x8 ECC and x32 DATA (codeword). A configuration of codeword x8 ECC and x32 DATA, illustrated in, is implemented by x4 memory chips having the same input/output width. The memory module includes two x4 memory chips for x8 ECC and eight x4 memory chips for x32 DATA. Configurations of the x8 ECC and x32 DATA, illustrated in, are implemented by x8 memory chips having the same input/output width. The memory module includes one x8 memory chip for x8 ECC and four x8 memory chips for x32 DATA.

The memory module, illustrated in, may perform a maximum of x4 data lane correction per sub-channel. The memory module, illustrated in, may simultaneously operate two ranks during correction of an x8 data lane to cause deteriorations in performance resulting from burst chopping (lockstep). For example, when mainstream DRAM density is increased to 16 Gb in a DDR5 RAM, an 8 Gb configuration may cause degradation in performance because the number of banks is decreased by half. The x4 and x8-based DIMMs, each having a basic capacity of 16 G, may make it difficult to configure a low capacity such as 8 Gb or 16 Gb. The x4 DIMM has a minimum capacity of 32 Gb, and the x8 DIMM has a minimum capacity of 16 Gb. Accordingly, a single rank may be used in configuring a minimum capacity. For this reason, rank interleave may not be possible, and thus, degradation in performance may occur.

illustrates a memory moduleaccording to an exemplary embodiment of the inventive concept. Referring to, the memory module (DIMM)is implemented to respectively input and output x8 ECC and x32 DATA to two sub-channels SCH-A and SCH-B using memory chips such as an x8 DRAM and an x16 DRAM having different input/output widths from each other.

The first sub-channel SCH-A includes two first memory chipsA andA and one second memory chipA.

Each of the first memory chipsA andA may be implemented to store data. In an exemplary embodiment, each of the first memory chipsA andA is implemented to have a first input/output width of x16. In an exemplary embodiment, the second memory chipA is implemented to have a second input/output width of x8. The second input/output width of x8 is half of the first input/output width x16. However, it is to be understood that the second input/output width is not limited thereto. For example, in response to each clock pulse of the clock signal CK, the first memory chipA can output 16 bits while the second memory chipA outputs 8 bits.

In an exemplary embodiment, each of the first memory chipsA andA and the second memory chipA have the same storage capacity.

The second sub-channel SCH-B includes two first memory chipsB andB and one second memory chipB. The second sub-channel SCH-B may have the same configuration as the first sub-channel SCH-A.

illustrates a system channel CH according to an exemplary embodiment of the inventive concept. Referring to, a system channel CH includes a first sub-channel SCH-A and a second sub-channel SCH-B. The first sub-channel SCH-A and the second sub-channel SCH-B may share data lanes DQ and may independently perform channel operations depending on commands (read and write commands) CMD_A and CMD_B.

illustrates an address depth of a memory chip in a memory moduleaccording to an exemplary embodiment of the inventive concept, andillustrates an addressing table of a memory chip housing the memory moduleaccording to an exemplary embodiment of the inventive concept.

Referring to, both a data chip (a first memory chip) and an ECC chip (a second memory chip) receive k+1 address bits ADD1 to ADDk+1 of the address ADD. In general, a chip size (storage capacity) is determined by an input/output width (the number of DQ pins) and an address depth. The term “address depth” refers to the number of address bits (a cycle count) counted (or cared) to determine a chip size. For example, the address depth may refer to the number of address bits considered or the number of address bits that are not ignored.

In an exemplary embodiment of the inventive concept, an address depth of a data chip is less than an address depth of an ECC chip. Although both the data chip and the ECC chip receive the same number of address bits in the memory module, the data chip does not count (or does not consider) at least one of the received address bits.

For example, as illustrated in, the data chip does not count (or does not consider) a single address bit ADDj+1 among the received address bits. For example, the data chip ignores ones of the received address bits. Accordingly, an address depth of the data chip is k, and an address depth of the ECC chip is k+1. For example, the data chip is accessed by k address bits counted, and the ECC chip is accessed by k+1 address bit counted. In an exemplary embodiment, an address includes k+1 address bits, the ECC chip is accessed using first to k+1-th address bits ADD1 to ADDk+1, and the data chip is accessed using first to j-th address bits ADD1 to ADDj and j+2-th to k+1-th address bits ADDj+2 to ADDk+1.

In an exemplary embodiment, the number of bits of an address, counted by the ECC chip, is greater than the number of bits of an address counted by the data chip. For example, the ECC chip considers more bits of the address than the data chip. In an exemplary embodiment, the number of bits of a bank group address, counted by the ECC chip, is greater than the number of bits of a bank group address counted by the data chip. In an exemplary embodiment, the ECC chip considers more bits of a bank group address than the data chip.

illustrates an address configuration of memory chips constituting storage capacity of 16 Gb. As illustrated in, an x8 memory chip (a first memory chip) and an x16 memory chip (a first memory chip) are different in presence or absence of a least significant bit BGof a bank group address and the number of banks.

In an exemplary embodiment of the inventive concept, each of the first memory chipsA,A,B,B (see) may be accessed by an addressing table including 2 bits of a bank group address, 2 bits of a bank address, 16 bits of a row address, and 10 bits of a column address, respectively.

In an exemplary embodiment, each of the second memory chipsA andB (see) may be accessed by an addressing table including 3 bits of a bank group address, 2 bits of a bank address, 16 bits of a row address, and a 10 bits of column address.

In an exemplary embodiment, the least significant bit BGof the bank group address is activated only in an x8 memory chip. In an exemplary embodiment, the x16 memory chips do not count the least significant bit BGof the bank group address. For example, an x16 memory chip may ignore the least significant bit BGof the bank group address. The memory systemaccording to an exemplary embodiment secures an x8 ECC lane when the least significant bit BGof the bank group is in a low-level during an error correction operation, and secures an x16 ECC lane when the least significant bit GBof the bank group transitions from a low-level L to a high-level H during the error correction operation.

illustrates a data output of the memory moduledepending on an error correction mode according to an exemplary embodiment of the inventive concept.

In an exemplary embodiment, when a least significant bit BGof a bank group address is in a low-level L, a reading operation depending on a first error correction mode is performed. In the first error correction mode, x8 ECC bits and x16 DATA bits may be output from an x8 memory chip and x16 memory chips in response to a reading command Read, respectively.

When the signal of the least significant bit BGof the bank group address is low-level L, x8 ECC bits and x16 DATA bits may be output from the x8 memory chip and the x16 memory chips in response to a first reading command Read1, respectively. In an exemplary embodiment, when the least significant bit BGof the bank group address transitions from the low-level L to the high-level H, a reading operation depending on a second error correction mode is performed. In response to a second reading command Read2, x8 ECC bits and x16 DATA bits may be output from the x8 memory chip and the x16 DATA memory chips, respectively. Accordingly, parities of the x16 ECC lane may be output from the x8 memory chip based on the first and second reading commands Read1 and Read2.

In an exemplary embodiment, the x8 memory chip (the second memory chip) may use a defective memory chip (employing a half chip) fixing the least significant bit BGof the bank group address to the low-level L or fixing the bank group address BGto the high-level H.

The memory moduleincludes heterogeneous first and second memory chips having the same storage capacity (for example, 16 Gb), as illustrated in. The first memory chip has an x16 input/output width, and the second memory chip has an x8 input/output width. However, the configuration of the memory module according to embodiments of the present disclosure is not limited thereto. Heterogeneous memory chips, having the same storage capacity, may be configured in various combinations.