Bypass switching arrangement for series connected switched capacitor regulators

This application isa continuation application of U.S. patent application Ser. No. 17/407,103, filed Aug. 19, 2021, now U.S. Pat. No. RE49,763, issued Dec. 19, 2023, which is a reissue of U.S. Pat. No. 10,389,244, issued Aug. 20, 2019, which isa continuation application of U.S. patent application Ser. No. 14/508,229, titled “A Hybrid Regulator Including a Buck Converter and a Switched Capacitor Converter,” filed on Oct. 7, 2014, by Le et al.,now U.S. Pat. No. 9,601,988,which claims the benefit of the earlier priority date of U.S. Provisional Patent Application No. 61/887,581, entitled “APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING FEEDBACK CONTROL IN HYBRID VOLTAGE REGULATORS,” filed on Oct. 7, 2013, by Le et al.,and is also reissue of U.S. Pat. No. 10,389,244, issued Aug. 8, 2019,each of which is expressly incorporated herein by reference in its entirety.

This invention was made with government support under 1248828 and 1353640 awarded by the National Science Foundation (NSF). The government has certain rights in the invention.

The present disclosure relates to feedback control in hybrid voltage regulators.

There is a strong demand to reduce the size of electronic systems. The size reduction is especially desirable in mobile electronic devices in which the space is a premium, but is also desirable in servers that are placed in big data centers since it is important to squeeze in as many servers as possible in a fixed real estate.

One of the largest components in electronic systems is a voltage regulator (also referred to as a power regulator). A voltage regulator can include a semiconductor chip, such as a DC-DC regulator chip, that delivers voltage from a voltage source (e.g., a battery) to an output load. The output load can include a variety of integrated chips (e.g., an application processor, a processor, a memory device, such as a dynamic read access memory (DRAM) and a NAND flash memory, radio-frequency (RF) chips, WiFi combo chips, and power amplifiers) in an electronic device. Unfortunately, a voltage regulator can include many bulky electronic components. Since each integrated chip may need a dedicated voltage regulator, it is desirable to reduce the size of the voltage regulators in electronic systems.

A voltage regulator can include a switched-inductor regulator. A switched-inductor regulator transfers charges from the power source to the output load using an inductor. A switched-inductor regulator can use power switches to connect/disconnect the inductor to one of multiple voltages, and provide an output voltage that is a weighted average of the multiple voltages. A switched-inductor regulator can adjust the output voltage by controlling the amount of time the inductor is coupled to one of the multiple voltages.

Unfortunately, a switched-inductor regulator is often not suitable for highly integrated electronic systems. The conversion efficiency of a switched-inductor regulator depends on the quality and size of the inductor, in particular when the power conversion ratio is high and when the amount of current consumed by the output load is high. Because an inductor can occupy a large area and is bulky to integrate on-die or on-package, existing switched-inductor regulators often use a large number of off-chip inductor components. This strategy often requires a large area on the printed circuit board, which in turn increases the size of the electronic device. The challenge is exacerbated as mobile system-on-chips (SoCs) become more complex and need increasingly larger number of voltage domains to be delivered by the voltage regulator.

Some embodiments of the disclosed subject matter include a voltage regulator system. The voltage regulator system includes a hybrid regulator configured to convert an input voltage to an output voltage, wherein the hybrid regulator comprises a plurality of voltage regulators including at least a switched-inductor regulator and a switched-capacitor regulator, and wherein the switched-inductor regulator is configured to operate in a discontinuous conduction mode. The voltage regulator system can also include a first feedback system configured to compare the output voltage to a reference voltage to determine a first operating frequency of the switched-inductor regulator and a second operating frequency of the switched-capacitor regulator, cause the switched-inductor regulator to operate at the first operating frequency, and cause the switched-capacitor regulator to operate at the second operating frequency, thereby causing the hybrid regulator to provide the output voltage that is within a tolerance range of the reference voltage.

In any of the disclosed embodiments disclosed herein, the first feedback system can be configured to cause the switched-inductor regulator to operate at the first operating frequency by providing a first periodic signal having the first operating frequency to the switched-inductor regulator.

In any of the disclosed embodiments disclosed herein, the switched-inductor regulator comprises a multi-phase switched-inductor regulator having a plurality of regulator cells, and wherein the first feedback system can be configured to cause the switched-inductor regulator to operate at the first operating frequency by providing a plurality of periodic signals having the first operating frequency to the switched-inductor regulator, wherein the plurality of periodic signals are out-of-phase from one another.

In any of the disclosed embodiments disclosed herein, the feedback system comprises a feedback control that can be configured to generate a first periodic signal, based on the reference voltage and the output voltage, having the second operating frequency.

In any of the disclosed embodiments disclosed herein, the feedback system comprises a frequency divider that can be configured to receive the first periodic signal generated by the feedback control and to generate a second periodic signal having the first operating frequency, and wherein the feedback system can be configured to provide the first periodic signal to the switched-capacitor regulator and the second periodic signal to the switched-inductor regulator.

In any of the disclosed embodiments disclosed herein, the voltage regulator system can include a second feedback system that can be configured to determine a difference between a parasitic voltage drop and a target voltage drop of the switched-capacitor regulator and cause the switched-inductor regulator to adjust current provided to the switched-capacitor regulator based on the difference.

In any of the disclosed embodiments disclosed herein, the second feedback system can be configured to cause the switched-inductor regulator to adjust the current provided to the switched-capacitor regulator by adjusting one or more of a switching period, an active period, and a duty cycle D of the switched-inductor regulator.

In any of the disclosed embodiments disclosed herein, the first operating frequency can be a fraction of the second operating frequency.

In any of the disclosed embodiments disclosed herein, the voltage regulator system can include a plurality of bypass switches, wherein one of the bypass switches can be configured to couple an input node of a first voltage regulator and an output node of a second voltage regulator in the hybrid regulator.

In any of the disclosed embodiments disclosed herein, the voltage regulator system can include a control block configured to determine a status of the bypass switches based on one or more of: the input voltage of the hybrid regulator, the output voltage of the hybrid regulator, and a conversion ratio of the switched-capacitor regulator in the hybrid regulator.

Some embodiments of the disclosed subject matter include an electronic system. The electronic system can include a load chip comprising a power domain, wherein the power domain comprises a first input voltage terminal and a first ground terminal, and a voltage regulator system in accordance with any of the disclosed embodiments disclosed herein, wherein the voltage regulator system can be configured to provide the output voltage of the voltage regulator system to the first input voltage terminal of the load chip.

Some embodiments of the disclosed subject matter include a method of providing an output voltage based on an input voltage. The method includes providing a hybrid regulator configured to convert the input voltage to the output voltage, wherein the hybrid regulator comprises a plurality of voltage regulators including at least a switched-inductor regulator and a switched-capacitor regulator, and wherein the switched-inductor regulator can be configured to operate in a discontinuous conduction mode, comparing, at a first feedback system, the output voltage to a reference voltage to determine a first operating frequency of the switched-inductor regulator and a second operating frequency of the switched-capacitor regulator, causing, by the first feedback system, the switched-inductor regulator to operate at the first operating frequency, and causing, by the first feedback system, the switched-capacitor regulator to operate at the second operating frequency, thereby causing the hybrid regulator to provide the output voltage that can be within a tolerance range of the reference voltage.

In any of the disclosed embodiments disclosed herein, causing the switched-inductor regulator to operate at the first operating frequency comprises providing a first periodic signal having the first operating frequency to the switched-inductor regulator.

In any of the disclosed embodiments disclosed herein, the switched-inductor regulator comprises a multi-phase switched-inductor regulator having a plurality of regulator cells, and wherein causing the switched-inductor regulator to operate at the first operating frequency comprises providing a plurality of periodic signals having the first operating frequency to the switched-inductor regulator, wherein the plurality of periodic signals are out-of-phase from one another.

In any of the disclosed embodiments disclosed herein, the method further includes generating, at a feedback control in the feedback system, a first periodic signal having the second operating frequency based on the reference voltage and the output voltage.

In any of the disclosed embodiments disclosed herein, the method further includes receiving, at a frequency divider in the feedback system, the first periodic signal generated by the feedback control, generating, by the frequency divider, a second periodic signal having the first operating frequency, and providing the first periodic signal to the switched-capacitor regulator and the second periodic signal to the switched-inductor regulator.

In any of the disclosed embodiments disclosed herein, the method further includes determining a difference between a parasitic voltage drop and a target voltage drop of the switched-capacitor regulator, and causing the switched-inductor regulator to adjust current provided to the switched-capacitor regulator based on the difference.

In any of the disclosed embodiments disclosed herein, causing the switched-inductor regulator to adjust the current provided to the switched-capacitor regulator by adjusting one or more of: a switching period, an active period, and a duty cycle D of the switched-inductor regulator.

In any of the disclosed embodiments disclosed herein, the hybrid regulator system comprises a plurality of bypass switches, wherein one of the bypass switches can be configured to couple an input node and an output node of the one of the voltage regulators in the hybrid regulator.

In any of the disclosed embodiments disclosed herein, the method further includes determining a status of the bypass switches based on one or more of: the input voltage of the hybrid regulator, the output voltage of the hybrid regulator, and a conversion ratio of the switched-capacitor regulator in the hybrid regulator.

In the following description, numerous specific details are set forth regarding the apparatus, systems, and methods of the disclosed subject matter and the environment in which such apparatus, systems, and methods may operate, etc., in order to provide a thorough understanding of the disclosed subject matter. It will be apparent to one skilled in the art, however, that the disclosed subject matter may be practiced without such specific details, and that certain features, which are well known in the art, are not described in detail in order to avoid complication of the disclosed subject matter. In addition, it will be understood that the examples provided below are exemplary, and that it is contemplated that there are other apparatus, systems, and methods that are within the scope of the disclosed subject matter.

Modern electronic systems have been tightly integrated as a system-on-chip (SoC) that includes multiple processing cores and heterogeneous components (e.g., memory controllers, hardware accelerators) within a single chip. These SoCs often use a large number of voltage domains to power the heterogeneous components. Such a large number of voltage domains are often powered by a power management integrated circuit (PMIC), which provides a plurality of voltages using a plurality of off-chip voltage regulators. Unfortunately, a PMIC often uses bulky, discrete inductors and capacitors that consume a large amount of volume, which can be critical in portable electronic devices with limited available space.

Given the drawback of existing PMICs, there has been a surge of interest in building voltage regulators that use smaller discrete components or even integrated voltage regulators (IVRs) that integrate components in a single die. One of such voltage regulators includes a switching regulator.

1 1 FIGS.A-B 1 FIG.A 100 108 114 116 100 108 104 118 114 116 118 114 116 114 116 114 116 114 116 IN One class of a switching regulator includes a switched-inductor (SI) regulator, such as a buck regulator, a boost regulator, a flying buck regulator, or a flipped flying buck regulator disclosed in U.S. Utility patent application Ser. No. 14/250,970, titled “APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING A HYBRID POWER REGULATOR,” by Le et al., filed on Apr. 11, 2014, which is herein incorporated by reference in its entirety.illustrate a step-down switched-inductor (SI) regulator and its operation. The SI regulator can convert a high voltage to a lower voltage. As illustrated in, the SI regulatorcan include an inductorand two switches,. The SI regulatorcan connect a first terminal of the inductorto one of (1) a first voltage source Vand (2) a second voltage sourcethrough a set of power switches,. In some cases, the second voltage sourcecan include, but is not limited to, a ground voltage source. The power switches,can be turned on and off using external inputs. In some cases, the power switches,can be controlled so that the two switches are not turned on at the same time. The power switches,can include transistors. The transistors can include a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, the switchcan include a P-channel MOSFET transistor; the switchcan include an N-channel MOSFET transistor.

1 FIG.B 1 FIG.A 114 116 102 108 120 102 110 110 108 104 108 118 100 510 106 X IN X OUT OUT IN OUT IN X IN illustrates a signal diagram of the switched-inductor regulator in. As the power switches,turn on and off with a period T, the input of the inductor Vcan swing between 0 and Vwith a period T. The inductorand capacitoroperate as a low-pass filter that averages Vover time, thereby creating a signal at the regulator output Vwith a small voltage ripple. The output voltage Vcan depend on the amount of time the inductoris coupled to the first voltage source Vand the amount of time the inductoris coupled to the second voltage source. For example, the SI regulatorcan adjust the level of Vto VD+(0V) (1−D), where D, a number between 0 and 1, is the portion of time Vis coupled to V. D is also referred to as a duty cycle. The output load that consumes the currentcan be any type of an electronic device, including one or more of processors, memory (DRAM, NAND flash), RF chips, WiFi combo chips, and power amplifiers.

100 A power efficiency of the SI regulatorcan be computed as:

L O L L O LOSS LOSS 106 100 where Pindicates the power delivered to the output loadand Pindicates the output power of the SI regulator. Pcan be computed as follows: P=P−P, where Pincludes the amount of power losses during the voltage regulation process.

LOSS 100 108 100 106 112 100 106 108 108 100 108 108 108 108 108 100 One of the major power losses Passociated with a SI regulatorincludes a resistive power loss incurred by the parasitic resistance of the inductor. When the SI regulatordelivers power to the output loadby providing current, ideally, the SI regulatorprovides all of its output power to the output load. In this ideal configuration, the inductorhas zero resistance, and, therefore, the current through the inductorwould not dissipate any power. However, in a practical scenario, the SI regulatordissipates some of its output power internally at the inductor, primarily due to the resistance of the material forming the inductor. This undesirable, finite resistance of the inductoris referred to as a parasitic resistance of the inductor. The parasitic resistance can incur a resistive power loss since the parasitic resistance can cause the current through the inductorto dissipate energy. Therefore, the resistive power loss can reduce the power conversion efficiency of the SI regulator.

R L,RMS L L L,RMS L,RMS L,PP R L,PP 2 108 108 100 When the current alternates with a predetermined period T, then the resistive power loss can be computed as P=IR, where Ris the value of the parasitic resistance of the inductor, and Iis the root-mean square of the current through the inductor. Ican be reduced by reducing the peak-to-peak ripple of the inductor current (I120). Therefore, the SI regulatorcan reduce the resistive loss Pby reducing the peak-to-peak ripple of the inductor current I120

L,PP X IN C 100 100 122 114 116 114 116 102 122 100 122 2 There are two ways to reduce the peak-to-peak ripple of the inductor current I120. First, the SI regulatorcan be operated at a high frequency and reduce the period T of the SI regulator. However, this solution can increase the power consumed to charge and discharge the parasitic capacitance at the junctionbetween switches,. This capacitive power loss can be significant because the size of the switches,can be large, which increases the parasitic capacitance, and because the voltage swing on Vis large (e.g., 0V˜V). This capacitive power loss can be computed as follows: P=fCV, where C is the amount of the parasitic capacitance at the junction, f is the frequency at which the SI regulatorswitches, and V is the voltage swing at the junction.

100 108 108 Second, the SI regulatorcan use an inductorwith a high inductance value. However, this approach makes the inductoroccupy a large volume, which can be problematic in many electronic devices, including portable electronic devices.

IN OUT Another class of a switching regulator includes a switched-capacitor (SC) regulator. An SC regulator can use one or more capacitors, instead of inductors, to transfer charge from a power source Vto an output load V. An SC regulator can use power switches to couple or decouple one or more capacitors to one of multiple voltages over a period of time, thereby providing an output voltage that is a weighted average of the multiple voltages. The SC regulator can control the output voltage by changing the configuration and the sequence in which capacitors are coupled to one another. Oftentimes, it is easier to implement an SC regulator with a small form factor compared to implementing an SI regulator because capacitors generally have a higher quality (e.g., lower series resistance) compared with inductors, particularly in integrated implementations.

Unfortunately, efficiencies of SC regulators can degrade at output voltages that are not a predetermined fraction of the input voltage. For example, an SC regulator can achieve high efficiencies at ½, ⅓, ⅔, ⅖, ⅗ of the input voltage. However, the same SC regulator can fail to provide high efficiencies when the output voltage deviates from those values. This is a problem for many SoCs that operate within a continuous range of voltages, or a range of voltages in 5-10 mV steps.

2 Some of the challenges associated with the SI regulator and the SC regulator can be addressed using a hybrid regulator. The hybrid regulator can include both the SC regulator and the SI regulator in series. The hybrid regulator topology can maintain high efficiency across a wide output and input voltage range, even with small inductors and capacitors. The hybrid regulator topology can include two types of regulators: an SI regulator and an SC regulator that divides or boosts the input voltage into an M/N fraction of the input voltage, where M and N can be any number greater than zero. This approach can reduce the resistive loss of the switched inductor regulator even with a small inductor with a low inductance. Furthermore, the hybrid regulator topology can reduce the capacitive loss (CVf loss) of the switched inductor regulator by limiting the voltage swing across the switches.

2 FIG.A 2 FIG.A 200 206 208 210 illustrates a hybrid regulator topology in accordance with some embodiments.includes a hybrid regulatorthat includes two or more voltage converter stages,,connected in series (in this disclosure, the term voltage converter stage is used interchangeably with a voltage regulator, a regulator, a voltage converter, and a converter), where each voltage converter stage can include a voltage regulator (also known as a voltage converter). The voltage regulator can include an SI regulator or an SC regulator, comprising one or more switches connecting/disconnecting one or more inductors or one or more capacitors, respectively. A typical inductance of the inductor in the SI regulator can range from 100 pico-Henry to 5 micro-Henry and power switches in the SI regulator can typically have width/(minimum length) values of 1000 to 100,000. For example, in a 90 nm process technology, power switch widths typically range from 100 um to 10 mm. Switching frequencies typically range from 1 MHz to 500 MHz.

216 216 212 214 2 FIG.B IN_SC IN_SC OUT_SC In some embodiments, an SC regulator can include an N:M step-down voltage regulator, as illustrated in. The N:M regulatoris configured to reduce a received voltage Vto (M/N) Vto generate the output V. Some examples of N:M include 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 6:5, 7:1, 7:2, 7:3, 7:4, 7:5, 7:6, or any other suitable fractions. The fraction N:M can be determined based on the configuration of capacitors and switches during the voltage regulation process. The configuration of capacitors and switches can be reconfigured during the voltage regulation process to dynamically change the fraction N:M to different values (e.g., (N−1):M (N−2):M, N:(M−1), N:(M−2), (N−1):(M−1), etc.).

3 3 FIGS.A-B 3 FIG.A 3 FIG.B 322 100 322 104 324 100 324 310 114 116 108 IN TMP TMP OUT illustrates a hybrid regulator that includes an SC regulator and an SI regulator connected in series.includes an SC regulatorand an SI regulator. The SC regulatorcan convert the input voltage Vto V. Then the SI regulatorcan receive Vand regulate it to provide Vin fine steps using multiple power switches,and one or more inductors.illustrates the timing diagram of signals in the regulator.

322 104 324 100 302 324 104 122 IN TMP X TMP IN This hybrid regulator hinges on the fact that SC regulators are good at dividing voltages across predetermined fractional values and that SI regulators are good at regulating across a wide range of conversion ratios of output voltage and input voltage, in fine steps. For example, in a 12V-to-1V step-down regulator, the SC regulatorcan receive 12V at Vand provide a 1/6 step-down, thereby providing 2V at V. Subsequently, the SI regulatorcan provide a subsequent regulation to regulate 2V to 1V. Since this regulator reduces the voltage swing at Vto V, which can be substantially less than V, this regulator can reduce the capacitive power loss due to the parasitic capacitance at the junction.

A hybrid regulator, like any other voltage regulators, is coupled to a control system that controls the output voltage of the hybrid regulator. The control system can include a feedback system that controls the hybrid regulator so that the output voltage is within the tolerable error range from the target output voltage.

4 FIG. 1 2 TMP IN TMP TMP OUT TMP 1 2 TMP 1 2 412 1 408 414 2 410 406 1 408 1 408 2 410 408 410 406 412 414 406 408 410 1 2 408 410 412 414 Designing a feedback system for a hybrid regulator can be challenging, even compared to traditional regulators, because there can be a large number of regulators in the hybrid regulator. One challenge unique to controlling a hybrid regulator is that the control system has to balance the current being delivered at each stage of the hybrid regulator.illustrates a two-stage hybrid regulator in accordance with some embodiments. If the current I, being delivered through Converter, is smaller than the current Ibeing delivered through Converter, the output voltage Vof Convertercan keep decreasing and cause a large voltage across Converter(i.e., V−V) and small voltage across Converter(i.e., V−V). Depending on the intended operating voltage range of the two converter stages,, both converters can malfunction if Vdeviates too much from its intended value. On the other hand, if Iis larger than I, Vcan keep increasing and can make both converter stages,malfunction. Therefore, the control system has to control both Converterand Converter,in order to balance the currents Iand I. The control system could balance the current across multiple converter stages using a separate feedback system for each converter stage. However, as the number of converters in the hybrid regulator increases, the control system can quickly become very complex.

This disclosure introduces apparatus, systems, and methods for providing a hybrid regulator having a simple feedback system that is capable of balancing current across a plurality of converter stages in the hybrid regulator. The disclosed feedback system can balance the current delivered across multiple converter stages without having a separate feedback system dedicated to each converter stage in the hybrid regulator. To this end, each converter stage in the hybrid regulator can be configured to operate in a mode in which the disclosed feedback system can control the operating frequency of the converter stage to control the amount of current provided by the converter stage.

5 FIG.A In some embodiments, the hybrid regulator can include a plurality of converter stages, which may include one or more SC converters. In some cases, the output current of the SC converter (e.g., an amount of charge delivered to the output node per unit time) can depend on its operating frequency. For example, as illustrated with respect to, an SC converter is configured to provide a fixed amount of charge (also referred to as a charge packet or a packet) to an output node within a switching period. Therefore, the output current of the SC converter can be increased with a higher operating frequency (e.g., a shorter switching period); the output current of the SC converter can be reduced with a lower operating frequency (e.g., a longer switching period). In some embodiments, the amount of charge provided to the output by the SC converter can depend on (1) an amount of charge in the charge packet and (2) an operating frequency of the converter (i.e., a frequency at which the charge packet is provided to the output.) In some embodiments, the amount of charge provided to the output by the SC converter is a multiplication of (1) an amount of charge in the charge packet and (2) an operating frequency of the converter (i.e., a frequency at which the charge packet is provided to the output.)

In some embodiments, the SI converter can also be configured so that its output current depends on its operating frequency. For example, the SI converter can be configured to operate in a discontinuous conduction mode (DCM). The DCM refers to an operating mode of an SI converter in which current is delivered to an output in a discontinuous manner. In the DCM, the SI converter can deliver a fixed amount of charge (also referred to as a charge packet or a packet) to an output node within a switching period. For example, the SI converter can deliver a non-zero amount of charge for a first portion of the switching period and deliver zero amount of charge in a second portion of the switching period until the next cycle. Therefore, the SI converter can increase the operating frequency (e.g., reduce the switching period) to deliver more charge (e.g., more current) to the output node or decrease the operating frequency to deliver less charge (e.g., less current) to the output node. In some embodiments, the amount of charge provided to the output by the SI converter in a DCM can depend on (1) an amount of charge in the charge packet and (2) an operating frequency of the converter (i.e., a frequency at which the charge packet is provided to the output.) In some embodiments, the amount of charge provided to the output by the SI converter in a DCM is a multiplication of (1) an amount of charge in the charge packet and (2) an operating frequency of the converter (i.e., a frequency at which the charge packet is provided to the output.)

When all SI converters in a hybrid regulator operates in a DCM, the feedback system of the hybrid regulator can control the operating frequency of converter stages in the hybrid regulator to balance the amount of current provided by each converter stage. As discussed above, the amount of charge provided to the output by the SI converter in a DCM or the SC converter can depend on (1) an amount of charge in the charge packet and (2) an operating frequency of the converter (i.e., a frequency at which the charge packet is provided to the output). Therefore, if the amount of charge in a charge packet of each converter stage is known in advance, then the feedback system can control the operating frequency of the converters to balance the amount of current provided by each converter stage.

For example, if the amount of charge in the charge packet is identical across the converter stages, then the feedback system can provide the same operating frequency to all converter stages to balance the current across the converter stages. As another example, consider a hybrid regulator with four regulators, and the amount of charge per charge packet in each regulator is 1, 2, 3, and 4, respectively. To balance charge across the four converter stages, the feedback system can determine an operating frequency of the four converter stages so that a multiplication of the operating frequency and the charge per packet is identical across the four converter stages. Therefore, the feedback system can determine that the operating frequencies in the four converter stages should be 12f, 6f, 4f, and 3f, where f is a scale factor.

In some embodiments, the feedback system can change the operating frequency of converter stages to change the amount of current provided by the hybrid regulator to the output load. If the output load needs more current than the currently provided amount of current, the feedback system can simply increase the operating frequency of the converters; if the output load needs less current than the currently provided amount of current, the feedback system can decrease the operating frequency of the converters. Referring back to the example above, the feedback system can control the operating frequency of the four converter stages by controlling the value of the single scale factor f. For instance, the feedback system can increase “f” when the output load needs more current; the feedback system can decrease “f” when the output load needs less current. Since the feedback system can control an amount of output current by changing only a single scale factor f, the feedback system can be very simple.

5 FIG.A 5 FIG.A 502 512 512 512 504 SWITCH SWITCH SWITCH illustrates a charge transfer operation of an SC regulator in accordance with some embodiments. In some embodiments, the operation of the SC regulator mimics the DCM. For example, when the switching frequency is low enough compared to a time constant of the SC regulator, the output current provided by the SC regulator can be close to zero by the end of the switching cycle (e.g., a beginning of the next switching cycle). As illustrated in, an SC regulator can deliver a non-zero amount of chargeduring a first portion of the switching period Tand deliver a close-to-zero amount of charge during a second portion of the switching period T. This charge transfer operation can be repeated every switching period T, as illustrated by another charge packet. Therefore, the amount of charge provided by the SC regulator can be controlled by controlling the switching period (i.e., the operating frequency).

5 5 FIGS.B-C 5 FIG.B 5 FIG.C 5 FIG.B 5 FIG.C 510 512 512 512 508 512 SWITCH SWITCH SWITCH SWITCH illustrate a charge transfer operation of an SI regulator in accordance with some embodiments. An SI regulator can operate in one of two modes: a DCM and a continuous conduction mode (CCM).illustrates the charge transfer operation of an SI regulator in the DCM;illustrates the charge transfer operation of an SI regulator in the CCM. In a DCM (), the SI regulator can deliver a non-zero amount of chargethrough the inductor during a first portion of the predetermined period Tand deliver zero amount of charge during a second portion of the predetermined period T. This charge transfer operation can be repeated every predetermined period T, as illustrated by another charge packet. On the other hand, in a CCM (), the SI regulator can deliver a non-zero amount of charge through the inductor throughout the entire predetermined period Tand the current through the inductor does not stay at 0 A.

5 5 FIGS.B-C 508 510 512 512 SWITCH SWITCH In some embodiments, the SI regulator can operate in the DCM mode to allow a feedback system to control the amount of output charge of the SI regulator simply by controlling an operating frequency of the SI regulator. The amount of charge delivered incan be computed as Q=∫Idt, where I refers to an amount of output current provided by a regulator. For the SI regulator operating in a DCM, the charge is delivered in discrete packets,, and a predetermined number of packets (e.g., one packet) is delivered every switching period T. Therefore, the feedback system can control the amount of charge delivered to the output of the SI regulator by changing the switching period Tof the SI regulator.

SWITCH 512 5 FIG.D In contrast, for an SI regulator operating in a CCM, the charge is delivered continuously. In this case, changing the switching period Tdoes not change the amount of charge delivered to the output. For example, as illustrated in, even when the operating frequency of an SI regulator operating in a CCM is doubled, the amount of charge delivered by the SI regulator to the output remains the same. As a result, for an SI regulator operating in a CCM, the feedback control cannot change the switching frequency to control the amount of charge delivered to the output. Thus, in some embodiments, the SI regulator can operate in a DCM in order to allow the feedback system to control the output current simply by controlling an operating frequency of the SI regulator.

510 510 510 510 L L L L When an SI regulator is operating in a DCM, it can control the shape of the charge packetby adjusting the rise and fall time of the output current. These times are determined by I=1/L∫Vdt, where L is the inductance value of the inductor, Iis the inductor current, and Vis the voltage applied across the inductor. When there is a constant positive voltage applied across the inductor (e.g., in a buck converter, the voltage of an inductor node coupled to the switches is higher than the voltage of an inductor node coupled to the output), the inductor current increases linearly, which becomes the rising slope of the triangular charge packet. When there is a constant negative voltage applied across the inductor (e.g., in a buck converter, the voltage of an inductor node coupled to the switches is lower than the voltage of an inductor node coupled to the output), the inductor current decreases linearly, which becomes the falling slope of the triangular charge packet. The shape of the charge packetand amount of charge per packet can be determined by adjusting the voltage applied across the inductor and the time period of applying positive and negative voltages across the inductor.

6 FIG.A 400 408 410 637 408 410 408 410 st nd PH_SI PH_SC PH_SI PH_SC illustrates a hybrid regulator system in accordance with some embodiments. The hybrid regulator system includes a hybrid regulatorhaving a 1stage SI regulatorand a 2stage SC regulator, and a feedback system. In some embodiments, one or more of the SI regulatorand SC regulatorscan be a single-phase regulator. In other embodiments, one or more of the SI regulatorand SC regulatorscan be a multi-phase regulator having a plurality of regulator cells, where each regulator cell includes circuit elements that can independently convert an input voltage to an output voltage. The number of regulator cells in a multi-phase regulator can be equivalent to the number of phases provided by the multi-phase regulator. Nand Nindicate the number of phases of the SI regulator and the SC regulator, respectively, where Nand Ncan be any number from larger or equal to 1 with typical values ranging from 1 to 100. The regulator cells can be independently operated by clock signals that are out-of-phase from one another. For example, a first regulator of the multi-phase regulator cell can receive a first clock signal and a second regulator cell of the multi-phase regulator can receive a second clock signal, where the first clock signal and the second clock signal have the same frequency and are out of phase, for instance, by 180 degrees.

637 620 639 632 634 639 639 The feedback systemcan include one or more of a feedback control, a frequency modifier, and, in case the regulators in the hybrid regulator are multi-phase, multi-phase signal generators,. The frequency modifiercan include a frequency divider that receives a first periodic signal having a first frequency and generates a second periodic signal having a second frequency. The frequency divider can include a regenerative frequency divider, an injection-locked frequency divider, a digital divider, or a sigma-delta fractional-N synthesizer. The frequency modifiercan be configured to receive an input periodic signal and provide an output periodic signal. The frequency of the output periodic signal can be a fractional multiple of the frequency of the input periodic signal. For example, the frequency of the output periodic signal can be ½ of the frequency of the input periodic signal; the frequency of the output periodic signal can be ⅗ of the frequency of the input periodic signal; the frequency of the output periodic signal can be 7/5 of the frequency of the input periodic signal; the frequency of the output periodic signal can be identical to the frequency of the input periodic signal; or the frequency of the output periodic signal can be twice the frequency of the input periodic signal.

6 FIG.B 6 FIG.A 640 636 604 618 642 644 640 620 628 628 408 410 604 618 620 628 604 618 620 628 620 620 604 618 OUT REF TARGET CTRL CTRL OUT REF CTRL OUT REF CTRL OUT REF illustrates a flow diagram that illustrates an operation of the hybrid regulator system ofin accordance with some embodiments. In step, a comparatorcan determine whether Vis larger or smaller than V, which is the target output voltage Vof the hybrid regulator. In steps/, based on the result of the comparison in step, the feedback control blockcan adjust the frequency of V, where Vis a clock signal that determines the operating frequencies of the SI regulatorand SC regulator. If Vis larger than V, the feedback control blockdecreases the frequency of V. If Vis smaller than V, the feedback control blockincreases the frequency of V. The feedback control blockcan implement a linear control scheme, a non-linear control scheme, a lower-bound control scheme, a proportional-integral-derivative (PID) control scheme, or any other suitable control schemes for controlling the hybrid regulator. The feedback control blockcan include an oscillator, such as a voltage controlled oscillator, that is configured to generate a periodic signal based on the difference between the Vand the V.

652 639 628 622 628 628 410 408 639 637 622 628 CTRL CTRL_DIV CTRL CTRL CTRL CTRL In step, the frequency dividercan receive Vand generate V, which is a frequency divided version of Vhaving a different frequency compared to V. In some embodiments, where the SC regulatorand SI regulatorcan operate at the same frequencies (i.e., an amount of charge in the charge packet of the SI regulator is identical to an amount of charge in the charge packet of the SC regulator), the frequency dividercan be removed from the feedback system, in which case VDIVis identical to V.

646 628 622 632 634 626 624 408 410 410 408 632 634 646 648 CTRL CTRL_DIV SI PH_SI SC PH_SC In step, based on the clock signals Vand V, multi-phase generators,can generate interleaved signals CLK[N−1:0]and CLK[N−1:0]that drive multiple phases of the SI regulatorand SC regulator, respectively. In some embodiments, where the SC regulatorand the SI regulatorare single-phase regulators, the multi-phase generator blockscan be removed, and the method stepsandcan be skipped.

648 626 408 602 410 650 410 408 410 624 604 636 640 408 410 410 408 602 SI PH_SI IN_N:M SC PH_SC OUT IN_N:M nd nd nd In step, based on CLK[N−1:0], the SI regulatorcan deliver charge packets to the 2stage SC regulator via the node V, which is the input of the 2stage SC regulator. In step, the 2stage SC regulatorcan receive charges from the SI regulatorand switches the capacitors in the SC regulatorbased on CLK[N−1:0]to deliver current to the output V, which is sent to the comparatorto go back to the first step. If the charge per packet and switching frequencies of the SI regulatorand SC regulatorare identical, the charge delivered by the two regulators,can be balanced and Vcan stay at a predetermined value.

OUT REF OUT REF OUT OUT OUT REF OUT 604 618 604 618 616 408 410 604 604 604 618 616 408 410 604 Following these steps, the feedback can regulate the output voltage Vto be within a tolerance range of the reference voltage V. The tolerance range of the hybrid regulator can be predetermined. The tolerance range of the hybrid regulator can be ±0.1-5% of the target voltage in steady state and ±5-20% during load transient events when the load current fluctuates. If the output voltage Vdrops below the reference voltage Vdue to a surge in load current, the feedback system increases the operating frequencies of the SI regulatorand SC regulatorto increase the amount of current provided to the output Vto increase V. As discussed above, the increase in the operating frequencies of the converter stages increases the delivered current because charge packets, having a fixed amount of charge, are delivered to the output more frequently. On the other hand, if the output voltage Vspikes over the reference voltage Vdue to a drop in load current, the feedback system decreases the operating frequencies of the SI regulatorand SC regulatorto reduce the current provided to the output V.

6 FIG.C 6 FIG.C 408 410 408 410 639 PH_SI PH_SC FREQ FREQ FREQ FREQ shows a signal diagram that illustrates how the feedback system regulates the output voltage in accordance with some embodiments. For this particular illustration, the number of phases in the SI regulator(N) is 2; the number of phase in the SC regulator(N) is 4; and the ratio of operating frequencies of the SI regulatorand the SC regulator(N:M) is 1:1. Since N:Mis 1:1,illustrates a scenario in which the feedback system does not include the frequency divider block.

CTRL SI PH_SI SC PH_SC CTRL 628 620 632 634 626 624 628 As provided in the previous paragraph, Vis a clock signal with a frequency set by the feedback control block. The multi-phase generator blocks,generate clock signals CLK[N−1:0]and CLK[N−1:0]that are interleaved by 180 degrees and 90 degrees, respectively, based on V.

1 CTRL SI SC SI L 630 628 0 626 0 624 408 410 0 62 408 0 610 At time t, Vhas a first rising edge, which triggers CLK[]and CLK[]. These are signals that control the phases of SI regulatorand SC regulator, respectively. When CLK[]is triggered, the first phase of the SI regulatorswitches to deliver a packet of charge, creating a triangular waveform on I[].

2 CTRL SI SC SI SI SC SC SI L 632 628 1 626 1 624 408 410 1 626 0 626 1 624 0 624 1 626 408 1 610 At time t, Vhas a second rising edge, which triggers the signals CLK[]and CLK[]that control the second phases of the SI regulatorand SC regulator, respectively. CLK[]is 180 degrees out of phase from CLK[]and CLK[]is 90 degrees out of phase from CLK[]. Controlled by CLK[], the second phase of the SI regulatorswitches to deliver a packet of charge, creating a triangular waveform on I[].

3 CTRL SI SC L 634 628 0 626 2 624 408 410 408 0 610 At time t, Vhas a third rising edge, which triggers signals CLK[]and CLK[]that control the first phase of the SI regulatorand the third phase of the SC regulator, respectively. Note that since the SI regulatoronly has 2 phases, it has now come back to the first phase and delivers a charge packet through I[].

4 CTRL SI SC 5 1 4 636 628 1 626 3 624 408 410 638 At time t, Vhas a fourth rising edge, which triggers signals CLK[]and CLK[]that control the second phase of the SI regulatorand the fourth phase of the SC regulator, respectively. From time t, the feedback system repeats the process of time instances t-t.

In some embodiments, the first converter stage of the hybrid regulator can include an SI regulator and the second converter stage of the hybrid regulator can include an SC regulator. In other embodiments, the first converter stage of the hybrid regulator can include an SC regulator and the second converter stage of the hybrid regulator can include an SI regulator.

410 410 In some embodiments, in addition to the feedback system that balances the delivered charge across all converter stages to regulate the output voltage, the hybrid regulator system can include another feedback system that is configured to operate the SC regulatorat a configuration at which the SC regulatorcan achieve a high efficiency.

410 602 604 604 IN_N:M OUT OUT In ideal cases, the SC regulatoris able to step down the input voltage Vto an output voltage V, where the value of the output voltage Vis

OUT 604 However, in practice, the output voltage Vcan be limited to

410 (i.e., the maximum output voltage of the SC regulatoris limited to

SC_DROP SC_DROP OUT 604 where Vis a parasitic voltage drop caused by various non-ideal effects, such as a parasitic resistance of switches. Oftentimes Vcan be substantially small compared to the output voltage V(e.g., 0-200 mV in a 90 nm process).

410 410 The control system of the SC regulatorcan anticipate that the output voltage of the SC regulatorcannot be exactly

410 604 Therefore, instead, the controls system of the SC regulatorcan set the target output voltageof the SC regulator as

T_DROP where Vis the target voltage drop.

T_DROP TARGET SC_DROP T_DROP As Vis set to a value close to 0V, it becomes increasingly difficult for the SC regulator to match the target output voltage Vbecause the actual voltage drop Vcan be greater than the target voltage drop V, in which case the maximum output voltage of the SC regulator

can be less than the target output voltage

IN N:M OUT SC_DROP T_DROP TARGET T_DROP T_DROP OUT 604 For example, consider a case where the SC regulator is a 2:1 regulator and the input voltage Vis 2V. Ideally, the output voltage Vcan be 1V and the parasitic voltage drop Vcan be 0V. However, if the parasitic resistance of switches is 0.1Ω and the load current is 1 A, the parasitic voltage drop from the parasitic resistance is 0.1V. Therefore, the maximum output voltage of the SC regulator is 0.9V. In this case, unless the target voltage drop Vis equal to or higher than 0.1V, the SC regulator cannot match the target voltage V. This problem becomes more pronounced as the parasitic resistance increases or the load current increases. As a result, when target voltage drop Vis set at a large value, it becomes easier to guarantee a proper regulation of the output voltage across a wide range of parasitic values and load current. On the other hand, the efficiency of the SC regulator degrades as the target voltage drop Vincreases as the output Vdeviates from

T_DROP T_DROP Therefore, there is a trade-off between ease of regulation and conversion efficiency. Thus, it is desirable to set the target voltage drop Vso that it is large enough to regulate the output properly while small enough to reduce efficiency degradation. The second feedback system of the hybrid regulator can be configured to set the target voltage drop Vso that it is large enough to regulate the output properly while small enough to reduce efficiency degradation.

7 FIG.A 6 FIG.A 400 637 768 408 768 illustrates a hybrid regulator system having a second feedback system in accordance with some embodiments. Compared to, the hybrid regulator system includes, in addition to the hybrid regulatorand the first feedback system, a second feedback systemthat adjusts parameters of the SI regulatorto increase the regulator efficiency.

768 746 744 604 768 746 410 602 SC_DROP T_DROP OUT SC_DROP I_N:M The goal of the second feedback systemis to keep the parasitic voltage drop Vwithin a tolerance range of the target voltage drop V, which is typically 0 to 0.2V, to increase the SC regulator efficiency. Since the conversion ratio of the SC regulator (i.e., N and M) is known and Vis regulated by the first feedback system, the second feedback systemcan control Vof the SC regulatorby adjusting V.

IN_N:M 602 768 410 768 410 408 To adjust V, the second feedback systemcan control an amount of current provided to the input of the SC regulator. The second feedback systemcan control an amount of current provided to the input of the SC regulatorby adjusting parameters of the SI regulator.

7 FIG.B 408 768 408 752 756 SI SI illustrates parameters of the SI regulatoradjusted by the second feedback systemin accordance with some embodiments. The adjusted parameters of the SI regulatorcan include a switching period T(or Freq, which is equal to

408 748 752 754 748 602 768 408 602 748 754 756 602 768 408 602 748 754 756 ACTIVE SI ACTIVE IN_N:M IN_N:M ACTIVE SI IN_N:M IN_N:M ACTIVE SI which controls an operating frequency of the SI regulator; an active period T, which indicates a portion of Tduring which the SI regulator provides current to the SC regulator; and a duty cycle Dthat defines a portion of the active period Tduring which the SI regulator increases the current provided to the SC regulator. To increase V, the second feedback systemcan cause the SI regulatorto deliver more charge to Vby increasing T, duty cycle D, and/or Freq. To decrease V, the second feedback systemcan cause the SI regulatorto deliver less charge to Vby decreasing T, duty cycle D, and/or Freq.

768 754 772 772 710 772 772 772 L In some embodiments, the second feedback systemcan control the duty cycle Dusing a zero current sense block. The zero current sense blockcan be configured to sense a time instance at which the inductor current of the SI regulator Ireaches 0 A, and at that time instance, the zero current sense blockcan be further configured to prevent the inductor current from flowing through the inductor by disconnecting the inductor from one or more nodes that provide current to the inductor. In some embodiments, the zero current sense blockcan include (1) a resistor in series with the inductor and (2) a voltage comparator that detects a voltage induced by the inductor current across the resistor. In such embodiments, the resistor can be the inherent resistive component (e.g., equivalent series resistance (ESR)) of the inductor. In other embodiments, the resistor can have a low resistance in order to reduce power dissipation across the resistor. Other types of zero current sense block, which are readily available to a person of ordinary skill in the art, are also contemplated.

7 FIG.C 768 746 SC_DROP illustrates a flow diagram of the hybrid regulator and the second feedback system. The flow diagram describes how the second feedback control systemcontrols Vto increase the efficiency of the hybrid regulator.

772 764 768 746 744 746 742 748 754 756 746 744 774 742 748 754 756 746 744 776 742 748 754 756 742 SC_DROP T_DROP SC_DROP ACTIVE SI SC_DROP T_DROP ACTIVE SI SC_DROP T_DROP ACTIVE SI In step, the comparatorin the second feedback systemdetermines whether Vis larger or smaller than V, which is the target value of Vpredetermined by the hybrid regulator. Subsequently, based on the result of the comparison, the SC drop control blockadjusts T, duty cycle D, and/or Freq. For example, if Vis larger than V, then, in step, the SC drop control blockincreases one or more of the three parameters—T, duty cycle D, and Freq. On the other hand, if Vis smaller than V, then, in step, the SC drop control blockdecreases one or more of the three parameters—T, duty cycle D, and Freq. The SC drop control blockcan be implemented as a finite-state-machine (FSM).

778 628 622 632 626 408 CTRL CTRL_DIV SI PH_SI In step, based on the clock signals Vand V, the multi-phase generatorcan generate interleaved signals CLK[N−1:0]that drive multiple phases of the SI regulator.

648 408 602 626 650 410 408 624 604 IN SI PH_SI SC PH_SC OUT Subsequently, in step, as discussed above, the SI regulatordelivers charge packets to VN:Mbased on CLK[N−1:0]. In step, as discussed above, the SC regulatorreceives charge from the SI regulatorand switches based on CLK[N−1:0]to deliver charge to the output V.

780 604 602 OUT IN In step, based on V, VN:Mand the equation

770 746 764 772 SC_DROP the SC drop measure blockcalculates Vand provides it to the comparatorso that the comparator can iterate the process again from step.

4 7 FIGS.- 2 FIG. Althoughillustrates feedback systems for a two stage hybrid regulator, the disclosed feedback systems can be applied to any type of hybrid regulators as generally illustrated in.

8 FIG. 8 FIG. 806 808 810 812 814 816 In some embodiments, the hybrid regulator can include bypass switches coupled to one or more converter stages so that certain converters can be dynamically bypassed to improve the efficiency of the hybrid regulator.illustrates a hybrid regulator with bypass switches in accordance with some embodiments.includes a plurality of voltage converter stages,, . . . ,, and bypass switches,, . . . ,.

IN OUT 802 1 806 804 Suppose that Vis 12V, the converteris a 6:1 SC regulator and the target output Vis 1.9V. Recall that

IN_N:M OUT SC_DROP OUT 1 818 2 808 810 1 818 804 812 814 816 2 where Vis the input and Vis the output of an SC regulator. The output of converter806can be a value very close to 12V divided by 6, which is 2V. Assuming Vis 0.1V, which is acceptable for maintaining a high (i.e. up to 95%) efficiency of the SC regulator, the remaining converters (i.e., converterand converter N) can be bypassed to directly connect the output of converter806to the output V. In this case, the switchis “off” or disconnected and the remaining switchesare “on” or connected to bypass converterand converter N.

OUT IN OUT SC_DROP OUT SC_DROP 804 802 2 808 804 1 818 804 1 2 1 2 808 1 818 2 808 As another example, suppose that the target output voltage Vis 0.75V, and the input voltage Vis 12V, and the converteris a 2:1 SC regulator. One way to deliver the target output Vis to use the same 6:1 SC regulator (converter806) in the previous case. In this case, Vbecomes 1.25V since Vis 0.75V, instead of 1.9V. Because Vis large, the conversion efficiency of the hybrid regulator degrades significantly (i.e. the efficiency is limited to 37.5%, which is 0.75/2.0). A better way is to use two converters (e.g., the converterand the converter) in series instead of just converter. Since the converteris a 2:1 SC regulator, the output of converter806can be 1.9V, and the output of convertercan be

SC_DROP SC_DROP 1 808 2 818 1 2 812 814 816 1 2 assuming Vof the converter806and the converter808is 0.1V. This way, Vis limited to a small value for both the converterand the converter, and the conversion efficiency for both converters can be high (i.e. up to 83.8% in this example). To enable this configuration, switchesandare “off” and the remaining switchesare “on” to bypass the rest of the converters except convertersand.

822 820 824 822 822 In some embodiments, each converter stage can include a reconfigurable converter(e.g., an SC converter that can reconfigure its step-down ratio across values such as 2:1, 3:1, 4:1, 5:1) that has multiple inputs and outputs, and one or more switch matricesthat can choose an input and an output from those multiple signals. For example, the reconfigurable convertercan receive, as input voltages, 4V and 6V, and provide, as output voltages, 1V and 2V. The reconfigurable convertercan be reconfigured across conversion ratios of 4:1, 6:1, 2:1, 3:1, depending on the desired input and output values.

812 814 816 818 818 812 814 816 818 812 814 816 802 804 IN OUT In some embodiments, the control of the bypass switches,,can be performed by a controller. For example, the controllercan determine the status of the bypass switches,,, for instance, whether one or more of the bypass switches are “on” or “off.” The controllercan determine the status of the bypass switches,,based on one or more of: V, V, the conversion ratios of all SC regulator stages in the hybrid regulator, and the parasitic SC voltage drops of SC converter stages in the hybrid regulator.

818 812 814 816 802 902 1 2 3 818 637 768 IN OUT 9 FIG. In some embodiments, the controllercan determine the status of the bypass switches,,using a lookup table. The lookup table can list which switches should be turned on for various Vand V804 values.illustrates the lookup table for controlling the bypass switches in accordance with some embodiments. This lookup tableis configured to control a hybrid regulator having 3 converter stages, where converteris a 2:1 SC converter, converteris a 3:1 SC converter, and converteris an SI converter, and 0V parasitic SC voltage drop. In some cases, the controllercan be a part of the first feedback systemor a part of the second feedback system.

812 814 816 1 806 2 808 8 FIG. In some embodiments, the bypass switches,,can be arranged serially, as illustrated in. In some cases, each bypass switch in a serial arrangement can be configured to couple an input node and an output node of a single converter stage. In other cases, each bypass switch in a serial arrangement can be configured to couple an input node of a first converter stage and an output node of a second converter stage. For example, one bypass switch can be configured to couple an input node of the converterand the output node of the converter. In some embodiments, the bypass switches can be arranged as a switch matrix that collectively couples an input node of one converter stage and an output node of another converter stage. In some embodiments, the bypass switches can be arranged as a tree of switches that collectively couples an input node of one converter stage and an output node of another converter stage.

10 FIG. 1000 1002 1004 1006 1008 400 408 410 637 768 1000 The disclosed apparatus and systems can include a computing device.is a block diagram of a computing device in accordance with some embodiments. The block diagram shows a computing device, which includes a processor, memory, one or more interfaces, an accelerator, and a hybrid regulator systemhaving a plurality of converter stages, including the first stage converterand the second stage converter, the first feedback system, and the second feedback system. The computing devicemay include additional modules, fewer modules, or any other suitable combination of modules that perform any suitable operation or combination of operations.

1000 1006 1006 The computing devicecan communicate with other computing devices (not shown) via the interface. The interfacecan be implemented in hardware to send and receive signals in a variety of mediums, such as optical, copper, and wireless, and in a number of different protocols, some of which may be non-transient.

1008 1008 1008 1008 In some embodiments, the acceleratorcan be implemented in hardware using an application specific integrated circuit (ASIC). The acceleratorcan be a part of a system on chip (SOC). In other embodiments, the acceleratorcan be implemented in hardware using a logic circuit, a programmable logic array (PLA), a digital signal processor (DSP), a field programmable gate array (FPGA), or any other integrated circuit. In some cases, the acceleratorcan be packaged in the same package as other integrated circuits.

1000 In some embodiments, the computing devicecan include user equipment. The user equipment can communicate with one or more radio access networks and with wired communication networks. The user equipment can be a cellular phone having telephonic communication capabilities. The user equipment can also be a smart phone providing services such as word processing, web browsing, gaming, e-book capabilities, an operating system, and a full keyboard. The user equipment can also be a tablet computer providing network access and most of the services provided by a smart phone. The user equipment operates using an operating system such as Symbian OS, iPhone OS, RIM's Blackberry, Windows Mobile, Linux, HP WebOS, and Android. The screen might be a touch screen that is used to input data to the mobile device, in which case the screen can be used instead of the full keyboard. The user equipment can also keep global positioning coordinates, profile information, or other location information. The user equipment can also be a wearable electronic device.

1000 1000 1000 1000 1000 The computing devicecan also include any platforms capable of computations and communication. Non-limiting examples include televisions (TVs), video projectors, set-top boxes or set-top units, digital video recorders (DVR), computers, netbooks, laptops, and any other audio/visual equipment with computation capabilities. The computing devicecan be configured with one or more processors that process instructions and run software that may be stored in memory. The processor also communicates with the memory and interfaces to communicate with other devices. The processor can be any applicable processor such as a system-on-a-chip that combines a CPU, an application processor, and flash memory. The computing devicecan also provide a variety of user interfaces such as a keyboard, a touch screen, a trackball, a touch pad, and/or a mouse. The computing devicemay also include speakers and a display device in some embodiments. The computing devicecan also include a bio-medical electronic device.

It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting.

As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, systems, methods and media for carrying out the several purposes of the disclosed subject matter. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter may be made without departing from the spirit and scope of the disclosed subject matter, which is limited only by the claims which follow.