Shift register unit, gate driving circuit, display device and driving method

This is a National Phase Application filed under 35 U.S.C. 371 as a national stage of PCT/CN2018/123947, filed Dec. 26, 2018, an application claiming the benefit of Chinese Application No. 201810552885.4, filed May 31, 2018 and Chinese Application No. 201810151627.5, filed Feb. 14, 2018, the content of each of which is hereby incorporated by reference in its entirety.

Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device and a driving method.

In the display field, especially in an OLED (Organic Light-Emitting Diode) display panel, a gate driving circuit is currently integrated in a GATE IC. In an IC design, an area of a chip is a main factor affecting the cost of the chip, and how to effectively reduce the area of the chip is a major consideration for technical developers.

At least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, an output circuit, and a compensation selection circuit. The blanking input circuit is configured toinput a blanking input signal to a control node and toinput a blanking signal to a first node during a blanking period of a frame; the display input circuit is configured to input a display signal to the first node in a display period of the frame in response to a display input signal; the output circuit is configured to output a composite output signal to an output terminal under the control of a level of the first node; the compensation selection circuit is electrically coupled to the output terminal and configured to chargetheacontrol node with the composite output signal in response to a compensation selection control signal.

For example, in the shift register unit provided in an embodiment of the present disclosure, the composite output signal includes a first output signal and a second output signal, and in the display period of the frame, the output circuit is configured to output the first output signal to the output terminal under the control of the level of the first node; in the blanking period of the frame, the output circuit is configured to output the second output signal to the output terminal under the control of the level of the first node.

the blanking input circuit includes an isolation sub-circuit configured to input the blanking signal to the first node under the control of a level of the control node and a first clock signal; the isolation sub-circuit includes a third transistor and a fourth transistor, a gate of the third transistor is coupled to the control node, a first electrode of the third transistor receives the blanking signal, a second electrode of the of the third transistor is coupled to a first electrode of the fourth transistor, a gate of the fourth transistor is coupled to a first clock signal terminal to receive a first clock signal, and a second electrode of the fourth transistor is coupled to a first electrode of the fourth leakage prevention transistor, a gate of the fourth leakage prevention transistor is coupled to the first clock signal terminal to receive the first clock signal, and a second electrode of the fourth leakage prevention transistor is coupled to the first node; a first electrode of the twenty-first transistor is coupled to a second voltage terminal, a gate of the twenty-first transistor is coupled to the first node, and a second electrode of the twenty-first transistor is coupled to the first electrode of the fourth leakage prevention transistor. For example, in the shift register unit provided in an embodiment of the present disclosure, the shift register unit further includes a twenty-first transistor and a fourth leakage prevention transistor, which are configured to prevent leakage of charges at the first node;

For example, in the shift register unit provided in an embodiment of the present disclosure, in the display period of the frame, the compensation selection circuit is configured to charge the control node with the first output signal in response to the compensation selection control signal.

For example, in the shift register unit provided in an embodiment of the present disclosure, the output terminal includes a shift signal output terminal that outputs the composite output signal, and the compensation selection circuit includes a first transistor; a gate of the first transistor is coupled to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is coupled to the shift signal output terminal to receive the composite output signal, and a second electrode of the first transistor is coupled to the control node.

For example, in the shift register unit provided in an embodiment of the present disclosure, the blanking input circuitfurtherincludes: a charging sub-circuit configured to input the blanking input signal to the control node in response to a second clock signal; a storage sub-circuit configured to store the blanking input signal input by the charging sub-circuit; an isolation sub-circuit configured to input the blanking signal to the first node under the control of a level of the control node and a first clock signal..

For example, in the shift register unit provided in an embodiment of the present disclosure, the charge sub-circuit includes a second transistor, a gate of the second transistor is coupled to a second clock signal terminal to receive the second clock signal, a first electrode of the second transistor is coupled to a blanking input signal terminal to receive the blanking input signal, and a second electrode of the second transistor is coupled to the control node; the storage sub-circuit includes a first capacitor, a first electrode of the first capacitor is coupled to the control node, and a second electrode of the first capacitor is coupled to a first voltage terminal to receive a first voltage; the isolation sub-circuit includes a third transistor and a fourth transistor, wherein a gate of the third transistor is coupled to the control node, a first electrode of the third transistor is coupled to a third clock signal terminal to receive a third clock signal as the blanking signal, a second electrode of the third transistor is coupled to a first electrode of the fourth transistor, a gate of the fourth transistor is coupled to the first clock signal terminal to receive the first clock signal, and a second electrode of the fourth transistor is coupled to the first node..

For example, in the shift register unit provided in an embodiment of the present disclosure, the display input circuit includes a fifth transistor, a gate of the fifth transistor is coupled to a display input signal terminal to receive the display input signal, a first electrode of the fifth transistor is coupled to a second voltage terminal to receive a second voltage as the display signal, and a second electrode of the fifth transistor is coupled to the first node.

For example, in the shift register unit provided in an embodiment of the present disclosure, the output terminal further includes a pixel signal output terminal, the pixel signal output terminal outputs the composite output signal, and the output circuit includes a sixth transistor, a seventh transistor, and a second capacitor, a gate of the sixth transistor is coupled to the first node, a first electrode of the sixth transistor is coupled to a fourth clock signal terminal to receive a fourth clock signal as the composite output signal, and a second electrode of the sixth transistor is coupled to the shift signal output terminal; a gate of the seventh transistor is coupled to the first node, a first electrode of the seventh transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal as the composite output signal, and a second electrode of the seventh transistor is coupled to the pixel signal output terminal; a first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second electrode of the sixth transistor.

For example, the shift register unit provided in an embodiment of the present disclosure further includes a noise reduction circuit and a first control circuit. The output terminal further includes a pixel signal output terminal, and the pixel signal output terminal outputs the composite output signal; the first control circuit is configured to control a level of a second node under the control of the level of the first node; the noise reduction circuit is configured to reduce noise of the first node, the shift signal output terminal, and the pixel signal output terminal under the control of the level of the second node.

For example, in the shift register unit provided in an embodiment of the present disclosure, the first control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor, a gate and a first electrode of the eighth transistor are coupled together and configured to be coupled to a fourth voltage terminal to receive a fourth voltage, a second electrode of the eighth transistor is coupled to the second node; a gate and a first electrode of the ninth transistor are coupled together and configured to be coupled to a fifth voltage terminal to receive a fifth voltage, a second electrode of the ninth transistor is coupled to the second node; a gate of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the second node, and a second electrode of the tenth transistor is coupled to the first voltage terminal to receive the first voltage.

For example, in the shift register unit provided in an embodiment of the present disclosure, the noise reduction circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor, a gate of the eleventh transistor is coupled to the second node, a first electrode of the eleventh transistor is coupled to the first node, and a second electrode of the eleventh transistor is coupled to the first voltage terminal to receive the first voltage; a gate of the twelfth transistor is coupled to the second node, a first electrode of the twelfth transistor is coupled to the shift signal output terminal, and a second electrode of the twelfth transistor is coupled to the first voltage terminal to receive the first voltage; a gate of the thirteenth transistor is coupled to the second node, a first electrode of the thirteenth transistor is coupled to the pixel signal output terminal, and a second electrode of the thirteenth transistor is coupled to a third voltage terminal to receive a third voltage.

For example, the shift register unit provided in an embodiment of the present disclosure further includes a second control circuit. The second control circuit is configured to control the level of the second node in response to a blanking control signal.

For example, in the shift register unit provided in an embodiment of the present disclosure, the second control circuit includes a fourteenth transistor, and the blanking control signal includes a first clock signal; a gate of the fourteenth transistor is coupled to a first clock signal terminal to receive the first clock signal, a first electrode of the fourteenth transistor is coupled to the second node, and a second electrode of the fourteenth transistor is coupled to a first voltage terminal to receive the first voltage.

For example, the shift register unit provided in an embodiment of the present disclosure further includes a third control circuit. The third control circuit is configured to control the level of the second node in response to a display control signal.

For example, in the shift register unit provided in an embodiment of the present disclosure, the third control circuit includes a fifteenth transistor, and the display control signal includes the display input signal; a gate of the fifteenth transistor is coupled to a display input signal terminal to receive the display input signal, a first electrode of the fifteenth transistor is coupled to the second node, and a second electrode of the fifteenth transistor is coupled to a first voltage terminal to receive a first voltage.

For example, the shift register unit provided in an embodiment of the present disclosure further includes a blanking reset circuit, wherein the blanking reset circuit is configured to reset the first node in response to a blanking reset signal.

For example, in the shift register unit provided in an embodiment of the present disclosure, the blanking reset circuit includes a sixteenth transistor, a gate of the sixteenth transistor is coupled to the second clock signal terminal to receive the second clock signal as the blanking reset signal, a first electrode of the sixteenth transistor is coupled to the first node, and a second electrode of the sixteenth transistor is coupled to the first voltage terminal to receive the first voltage.

For example, the shift register unit provided in an embodiment of the present disclosure further includes a display reset circuit, and the display reset circuit is configured to reset the first node in response to a display reset signal.

For example, in the shift register unit provided in an embodiment of the present disclosure, the display reset circuit includes a seventeenth transistor, a gate of the seventeenth transistor is coupled to a display reset signal terminal to receive the display reset signal, a first electrode of the seventeenth transistor is coupled to the first node, and a second electrode of the seventeenth transistor is coupled to a first voltage terminal to receive a first voltage.

At least one embodiment of the present disclosure further provides a gate driving circuit including a plurality of shift register units, which are cascaded, and each of the shift register units is the shift register unit as above.

th th th th For example, the gate driving circuit provided by an embodiment of the present disclosure further includes a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line, in a case where the shift register unit includes a fourth clock signal terminal, the fourth clock signal terminal of the shift register unit of the (4n-3)stage is coupled to the first sub-clock signal line; the fourth clock signal terminal of the shift register unit of the (4n-2)stage is coupled to the second sub-clock signal line; the fourth clock signal terminal of the shift register unit of the (4n-1)stage is coupled to the third sub-clock signal line; the fourth clock signal terminal of the shift register unit of the (4n)stage is coupled to the fourth sub-clock signal line, where n is an integer greater than 0.

th th th For example, the gate driving circuit provided in an embodiment of the present disclosure further includes a fifth sub-clock signal line and a sixth sub-clock signal line; in a case where the shift register unit includes a second clock signal terminal and a third clock signal terminal, the second clock signal terminal of the shift register unit of the (2n-1)stage is coupled to the fifth sub-clock signal line, and the third clock signal terminal of the shift register unit of the (2n-1)stage is coupled to the sixth sub-clock signal line; the second clock signal terminal of the shift register unit of the (2n)stage is coupled to the sixth sub-clock signal line, and the third clock signal terminal is coupled to the fifth sub-clock signal line, where n is an integer greater than 0.

th th th th For example, in the gate driving circuit provided in an embodiment of the present disclosure, in a case where the shift register unit includes a blanking input signal terminal, a display input signal terminal, and a shift signal output terminal, the blanking input signal terminal of the shift register unit of the (n+1)stage is coupled to the shift signal output terminal of the shift register unit of the nstage; the display input signal terminal of the shift register unit of the (n+2)stage is coupled to the shift signal output terminal of the shift register unit of the nstage, where n is an integer greater than 0.

At least one embodiment of the present disclosure further provides a display device including any one of the gate driving circuits provided in the embodiments of the present disclosure.

At least one embodiment of the present disclosure further provides a driving method of a shift register unit, including:

a display period of a frame, including: a first input stage in which the display input circuit inputs the display signal to the first node in response to the display input signal; a first output stage in which the output circuit outputs a first output signal under the control of the level of the first node;

a blanking period of the frame, including: a second input stage in which the blanking input circuit inputs the blanking input signal to the control node and the blanking signal to the first node; a second output stage in which the output circuit outputs a second output signal under the control of the level of the first node; where the composite output signal comprises a first output signal and a second output signal.

For example, the driving method provided in an embodiment of the present disclosure further includes: the compensation selection circuit charges the control node with the first output signal in response to the compensation selection control signal during a display period of the frame.

th th th th At least one embodiment of the present disclosure further provides a driving method of a gate driving circuit, including: when the gate driving circuit drives a display panel, in a display period of any frame, the output terminal of the shift register unit of the nstage outputs a first output signal, and the compensation selection circuit in the shift register unit of the nstage charges the control node in the shift register unit of the nstage by using the first output signal in response to the compensation selection control signal; in a blanking period of the frame, the output terminal of the shift register unit of the nstage outputs a second output signal; where the composite output signal includes the first output signal and the second output signal, and n is an integer greater than 0.

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. Apparently, the described embodiments are only some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any creative labor, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of “first”, “second”, and similar terms in the present disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms “a”, “an”, or “the” and similar words do not denote a limitation of quantity, but rather denote the presence of at least one. The word “comprising”, “comprises”, and the like mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms “coupled” or “connected” and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words “upper”, “lower”, “left”, “right”, and the like are used merely to indicate relative positional relationships, and when an absolute position of an object being described is changed, the relative positional relationships may also be changed accordingly.

In the embodiments of the present disclosure, for example, in a case where the respective circuits are implemented as N-type transistors, the term “pull-up” means charging a node or an electrode of a transistor such that an absolute value of a level of the node or the electrode is raised, thereby implementing an operation (e.g., turning on) of the corresponding transistor; “pull-down” means discharging a node or an electrode of a transistor so that an absolute value of a level of the node or the electrode is lowered, thereby achieving an operation (e.g., turning off) of the corresponding transistor.

For another example, in a case where the respective circuits are implemented as P-type transistors, the term “pull-up” means discharging a node or an electrode of a transistor such that an absolute value of a level of the node or the electrode is lowered, thereby implementing an operation (e.g., turning on) of the corresponding transistor; “pull down” means charging a node or an electrode of a transistor such that an absolute value of a level of the node or the electrode is raised, thereby implementing an operation (e.g., turning off) of the corresponding transistor.

Also, specific meanings of the terms “pull-up” and “pull-down” will be adjusted accordingly depending on a specific type of transistor employed, as long as control of the transistor can be achieved to achieve a corresponding switching function.

At present, a gate driving circuit for an OLED is usually formed by combining three sub-circuits, namely a detection circuit, a display circuit and a connection circuit (or gate circuit) for outputting a composite pulse of the detection circuit and the display circuit, and such a circuit structure is very complex and cannot meet the requirements for high resolution and narrow bezel.

In a case where a compensation is performed on a sub-pixel unit in the OLED display panel, in addition to an internal compensation by providing a pixel compensation circuit in the sub-pixel unit, an external compensation may be performed by providing sensing transistors. When performing the external compensation, the gate driving circuit constituted by the shift register units needs to supply driving signals for scanning transistors and the sensing transistors, for example, scanning driving signals for the scanning transistors supplied n a display period (Display) of one frame, and sensing driving signals for the sensing transistors in a blanking period (Blank) of the frame, to the sub-pixel units in the display panel, respectively.

In one external compensation method, the sensing driving signals output by the gate driving circuit are used to sequentially scan row-by-row, for example, the sensing driving signal for the sub-pixel units of a first row in the display panel is output in the blanking period of a first frame, the sensing driving signal for the sub-pixel units of a second row in the display panel is output in a blanking period of a second frame, and so on, thus the sensing driving signals are sequentially output row-by-row at a frequency that one sensing driving signal corresponding to the sub-pixel units of one row is output per frame, that is, the progressive sequential compensation for the display panel is completed.

However, in a case where the above row-by-row sequential compensation method is adopted, there is a possibility that a display failure problem occurs: firstly, a scanning line moving row-by-row occurs in the process of scanning and displaying multiple frames; secondly, a difference of time points of performing the external compensation may cause brightness difference of different areas of the display panel to be relatively large, for example, when the externally compensation is performed on the sub-pixel units of the 100th row of the display panel, although the externally compensation has been already performed on the sub-pixel units of the 10th row of the display panel, the light emitting brightness of the sub-pixel units of the 10th row may have been changed, for example, the brightness is reduced, so that the brightnesses of different areas of the display panel may be de-uniform, and thus such a problem may be more obvious in a large-sized display panel.

In view of the above problems, at least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, an output circuit, and a compensation selection circuit. The blanking input circuit is configured to input a blanking input signal to a control node and to input a blanking signal to a first node during a blanking period of one frame; the display input circuit is configured to input a display signal to the first node in a display period of the frame in response to a display input signal; the output circuit is configured to output a composite output signal to an output terminal under the control of a level of the first node; the compensation selection circuit is electrically coupled with the output terminal and is configured to charge the control node by utilizing the composite output signal in response to a compensation selection control signal. The embodiments of the present disclosure also provide a gate driving circuit, a display device and a driving method corresponding to the shift register unit.

The shift register unit, the gate driving circuit, the display device and the driving method provided by the embodiments of the present disclosure can also realize a random compensation on the premise of considering the progressive sequential compensation (for example, the progressive sequential compensation is required in a shutdown detection), so that the display defects such as scanning line and de-uniform display brightness caused by the progressive sequential compensation can be avoided.

It should be noted that, in the embodiments of the present disclosure, the random compensation refers to an external compensation method different from the progressive sequential compensation method, and the sensing driving signal corresponding to the sub-pixel units of any row of the display panel can be randomly output in the blanking period of a certain frame, the following embodiments are the same as above, and are not described again.

In addition, in the embodiments of the present disclosure, “one frame”, “each frame”, or “a certain frame” includes a display period and a blanking period that are sequentially performed, for example, in the display period, the gate driving circuit outputs a display output signal that can drive the display panel to complete scanning and displaying of a complete image from the first row to the last row, and in the blanking period, the gate driving circuit outputs a blanking output signal that can be used to drive the sensing transistor in a certain row of sub-pixel units in the display panel to complete the external compensation of the certain row of sub-pixel units.

Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

10 10 100 200 300 400 100 200 300 1 FIG. At least one embodiment of the present disclosure provides a shift register unit, as shown in, the shift register unitincludes a blanking input circuit, a display input circuit, an output circuit, and a compensation selection circuit. The blanking input circuit, the display input circuit, and the output circuitare coupled together through a first node Q.

100 1 FIG. 2 FIG. The blanking input circuitis configured to input a blanking input signal to a control node H (not shown in, see) and to input a blanking signal to the first node Q in a blanking period of one frame.

100 1 1 100 In some embodiments, the blanking input circuitmay be coupled to a blanking input signal terminal STUand a second clock signal terminal CLKB, so that the blanking input signal input from the blanking input signal terminal STUmay be input to the control node H under the control of a second clock signal input from the second clock signal terminal CLKB. The blanking input circuitmay also be coupled to the third clock signal terminal CLKC so that a third clock signal input from the third clock signal terminal CLKC is input to the first node Q as a blanking signal in a blanking period of one frame, thereby pulling up a potential of the first node Q to an operating potential.

100 100 For example, the blanking input circuitmay receive and store the blanking input signal in a display period of one frame, and output the blanking signal to the first node Q in accordance with the blanking input signal in the blanking period of this frame, thereby pulling up the potential of the first node Q to the operating potential. For another example, the blanking input circuitmay receive and store the blanking input signal in the blanking period of the frame, and output the blanking signal to the first node Q according to the blanking input signal in a blanking period of a next frame, thereby pulling up the potential of the first node Q to the operating potential. The embodiments of the present disclosure are not limited above.

200 200 2 200 200 The display input circuitis configured to input a display signal to the first node Q in a display period of one frame in response to a display input signal. For example, in some embodiments, the display input circuitmay be coupled to a display input signal terminal STUto receive the display input signal, and the display input circuitmay be further coupled to a second voltage terminal VDD to receive a second voltage as the display signal. For example, the display input circuitmay input the display signal to the first node Q under the control of the display input signal in the display period of the frame, thereby pulling up the potential of the first node Q to the operating potential.

It should be noted that, in the embodiments of the present disclosure, the second voltage terminal VDD is configured to output a DC high level signal, that is, the second voltage is at a high level, and the following embodiments are the same and will not be described again.

300 300 The output circuitis configured to output a composite output signal to the output terminal OUTPUT under the control of the level of the first node Q. For example, in some embodiments, the output circuitmay be coupled to a fourth clock signal terminal CLKD to receive a fourth clock signal as the composite output signal.

300 300 For example, in some embodiments, the composite output signal includes a first output signal and a second output signal, e.g., the first output signal is a display output signal, and the second output signal is a blanking output signal. For example, in the display period of the frame, the output circuitoutputs the display output signal to the output terminal OUTPUT under the control of the level of the first node Q, for example, in some embodiments, the output terminal OUTPUT may include a shift signal output terminal CR and a pixel signal output terminal OUT, the display output signal output from the shift signal output terminal CR may be used for scan shift from a previous register unit to a next shift register unit, and the display output signal output from the pixel signal output terminal OUT may be used for driving the sub-pixel units in the display panel to perform scan display; in the blanking period of the frame, the output circuitoutputs a blanking output signal, which may be used to drive the sensing transistor, to the output terminal OUTPUT under the control of the level of the first node Q.

400 The compensation selection circuitis electrically coupled to the output terminal OUTPUT and is configured to charge the control node H by using the composite output signal in response to a compensation selection control signal.

400 For example, in some embodiments, the compensation selection circuitis configured to charge the control node H with a first output signal (e.g., the display output signal) in response to the compensation selection control signal during the display period of the frame.

400 400 For example, in a case where the output terminal OUTPUT includes the shift signal output terminal CR and the pixel signal output terminal OUT, in one example, the compensation selection circuitmay be electrically coupled to the shift signal output terminal CR. In some embodiments, the compensation selection circuitmay also be coupled to a compensation selection control terminal OE to receive the compensation selection control signal.

400 400 400 400 100 400 300 th th th th For example, when performing the progressive sequential compensation, the compensation selection circuitmay be disabled by inputting a signal to turn off the compensation selection circuitthrough the compensation selection control terminal OE. In another example, when performing the random compensation, in a case where the nrow of sub-pixel units in the display panel needs to be compensated in a certain frame, in the display period of the frame, when the output terminal OUTPUT outputs the display output signal (the composite output signal) for driving the nrow of sub-pixel units, the compensation selection control signal for turning on the compensation selection circuitmay be input through the compensation selection control terminal OE, and the compensation selection control signal may be configured to have the same timing as the above-described display output signal for driving the nrow of sub-pixel units; meanwhile, since the compensation selection circuitis electrically coupled to the output terminal OUTPUT, the control node H in the compensation input circuitmay be charged with the composite output signal when the compensation selection circuitis turned on, so that the control node H is charged to a high level, and thus the output circuitmay output the blanking output signal for driving the sensing transistors in the sub-pixel units of the nrow in the blanking period of the frame.

400 In some embodiments, the compensation selection control terminal OE may be configured to be electrically coupled to a control circuit, which may provide an electrical signal for turning on or off the compensation selection circuitto the compensation selection control terminal OE. For example, in one example, the control circuit may be implemented as an FPGA (field programmable gate array) device or any other signal generation circuit.

10 400 According to the shift register unitprovided in the embodiment of the present disclosure, with the compensation selection circuit, the random compensation can be achieved on the premise of achieving the progressive sequential compensation, so that display defects such as scanning lines and non-uniformity of display brightness due to progressive sequential compensation can be avoided.

2 100 110 120 130 In one example of an embodiment of the present disclosure, as shown in FIG., the blanking input circuitincludes a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit.

110 110 1 110 110 The charging sub-circuitis configured to input the blanking input signal to the control node H in response to the second clock signal. For example, the charging sub-circuitis coupled to the blanking input signal terminal STUto receive the blanking input signal, and the charging sub-circuitis coupled to the second clock signal terminal CLKB to receive the second clock signal. For example, the charging sub-circuitmay be turned on under the control of the second clock signal to input the blanking input signal to the control node H.

120 110 120 The storage sub-circuitis configured to store the blanking input signal input by the charging sub-circuit. For example, in the display period of the frame, the control node H is charged to a high level by the input blanking input signal, and the storage sub-circuitmay store the blanking input signal so that the high level of the control node H is maintained up to the blanking period of the frame.

130 130 130 The isolation sub-circuitis configured to input the blanking signal to the first node Q under the control of the level of the control node H and the first clock signal. For example, in some embodiments, the isolation sub-circuitis coupled to the first clock signal terminal CLKA to receive the first clock signal, and the isolation sub-circuitis coupled to the third clock signal terminal CLKC to receive the third clock signal as the blanking signal.

130 130 130 For example, in the blanking period of the frame, the isolation sub-circuitis turned on under the control of the level of the control node H and the first clock signal, so that the blanking signal may be input to the first node Q. For another example, in some embodiments, the isolation sub-circuitis disposed between the first node Q and control node H for preventing interaction of the first node Q and the control node H. For example, the isolation sub-circuitmay disconnect the first node Q from the control node H when the blanking signal is not required to be output.

10 100 200 100 200 300 According to the shift register unitprovided by the embodiments of the present disclosure, it is possible to control the level of the first node Q at different periods through the blanking input circuitand the display input circuitrespectively, so that the blanking input circuitand the display input circuitshare the same output circuitto realize the output of the composite output signal.

3 FIG. 10 600 600 600 1 1 In some embodiments, as shown in, the shift register unitmay further include a first control circuit, and the first control circuitis configured to control a level of a second node QB under the control of the level of the first node Q. For example, in one example, the first control circuitis coupled to a first voltage terminal VGLand a fourth voltage terminal VDD_A, It should be noted that, in the embodiment of the disclosure, for example, the first voltage terminal VGLmay be configured to provide a DC low level signal, and the following embodiments are the same and will not be described again.

600 1 600 For example, when the first node Q is at a high level, the first control circuitmay pull down a potential of the second node QB to a low level through the first voltage terminal VGL. For another example, when the potential of the first node Q is at a low level, the first control circuitmay charge the second node QB with a fourth voltage (e.g., at a high level) input from the fourth voltage terminal VDD_A to pull up the second node QB to a high level.

600 In another example, the first control circuitmay be further coupled to a fifth voltage terminal VDD_B to receive a fifth voltage (e.g., at a high level), for example, the fourth voltage terminal VDD_A and the fifth voltage terminal VDD_B may be configured to alternately output a high level, that is, when the fourth voltage terminal VDD_A outputs a high level, the fifth voltage terminal VDD_B outputs a low level, and when the fourth voltage terminal VDD_A outputs a low level, the fifth voltage terminal VDD_B outputs a high level.

3 FIG. 10 500 500 500 1 500 1 500 In some embodiments, as shown in, the shift register unitmay further include a noise reduction circuit, and the noise reduction circuitis configured to reduce noise of the first node Q and the output terminal OUTPUT under the control of the level of the second node QB. For example, the noise reduction circuitis coupled to the first voltage terminal VGL, and when the noise reduction circuitis turned on under the control of the level of the second node QB, the first node Q and the Output terminal OUTPUT may be pulled down by the first voltage terminal VGL, thereby reducing the noise of the first node Q and the output terminal OUTPUT. In a case where the output terminal OUTPUT includes the shift signal output terminal CR and the pixel signal output terminal OUT, the noise reduction circuitmay simultaneously perform noise reduction on the shift signal output terminal CR and the pixel signal output terminal OUT.

3 FIG. 10 700 700 700 1 700 1 100 In some embodiments, as shown in, the shift register unitmay further include a second control circuit, and the second control circuitis configured to control the level of the second node QB in response to the blanking control signal. For example, in one example, the second control circuitis coupled to the first clock signal terminal CLKA to receive the first clock signal as the blanking control signal, while being coupled to the first voltage terminal VGLto receive the first voltage at a low level. For example, in the blanking period of the frame, the second control circuitmay be turned on in response to the first clock signal, so that the second node QB may be pulled down by the first voltage terminal VGL. In this way, the influence of the second node QB on the first node Q in the blanking period can be reduced, so that the blanking input circuitcharges the first node Q more sufficiently.

700 It should be noted that, in the embodiments of the present disclosure, the second control circuitmay also be coupled to other signal terminals to receive the blanking control signal, which is not limited by the present disclosure.

3 FIG. 10 800 800 800 2 1 200 800 800 1 200 In some embodiments, as shown in, the shift register unitmay further include a third control circuit, and the third control circuitis configured to control the level of the second node QB in response to the display control signal. For example, in one example, the third control circuitis coupled to the display input signal terminal STUto receive the display input signal as the display control signal, and is coupled to the first voltage terminal VGLto receive the first voltage at the low level. For example, in the display period of the frame, while the display input signal is supplied to the display input circuitto charge the first node Q, the display input signal is also supplied to the third control circuit, the third control circuitis turned on, so that the second node QB can be pulled down through the first voltage terminal VGL. In this way, the influence of the second node QB on the first node Q can be reduced in the display period, so that the first node Q is charged more sufficiently by the display input circuit.

800 It should be noted that, in the embodiments of the present disclosure, the third control circuitmay also be coupled to other signal terminals to receive the display control signal, which is not limited by the present disclosure.

3 FIG. 10 900 900 900 1 900 1 900 1 In some embodiments, as shown in, the shift register unitmay further include a blanking reset circuit, and the blanking reset circuitbeing is configured to reset the first node Q in response to a blanking reset signal. For example, in one example, the blanking reset circuitmay be coupled to the second clock signal terminal CLKB to receive the second clock signal as the blanking reset signal, while being coupled to the first voltage terminal VGLto receive the first voltage at a low level. For example, before the display period of the frame, the blanking reset circuitmay be turned on in response to the second clock signal, so that the first node Q may be reset through the first voltage terminal VGL; for another example, in the blanking period of the frame, the blanking reset circuitmay be turned on in response to the second clock signal, so that the first node Q may be reset through the first voltage terminal VGL.

900 900 It should be noted that, in the embodiments of the present disclosure, in addition to the second clock signal, the blanking reset circuitmay also use other control signals as the blanking reset signal, for example, the blanking reset circuitmay also be coupled to other signal terminals to receive the blanking reset signal, which is not limited by the present disclosure.

3 FIG. 10 1000 1000 1000 1 1000 1 10 10 th In some embodiments, as shown in, the shift register unitmay further include a display reset circuit, and the display reset circuitis configured to reset the first node Q in response to a display reset signal. For example, in one example, the display reset circuitmay be coupled to a display reset signal terminal STD to receive the display reset signal, while being coupled to the first voltage terminal VGLto receive the first voltage of the low level. For example, in the display period of the frame, the display reset circuitmay be turned on in response to the display reset signal, so that the first node Q may be reset through the first voltage terminal VGL. For example, for the shift register unitof the nstage, the display reset signal terminal STD thereof may be coupled to a shift signal output terminal CR of the shift register unitof a next stage.

10 500 600 700 800 900 1000 3 FIG. It will be understood by those skilled in the art that although the shift register unitinshows to include the noise reduction circuit, the first control circuit, the second control circuit, the third control circuit, the blanking reset circuitand the display reset circuit, the above examples do not limit the scope of the present disclosure. In practical applications, a skilled person may choose to use or not use one or more of the above circuits according to circumstances, and various combined modifications based on the above circuits do not depart from the principle of the present disclosure, and are not described in detail here.

10 10 1 17 1 2 3 FIG. 4 FIG. 4 FIG. 4 FIG. In one example of the embodiment of the present disclosure, the shift register unitshown inmay be implemented as the circuit configuration shown in. As shown in, the shift register unitincludes: first to seventeenth transistors M-Mand first and second capacitors Cand C. The output terminal OUTPUT includes a shift signal output terminal CR and a pixel signal output terminal OUT, both of which can output a composite output signal. Note that the transistors shown inare all described by taking N-type transistors as an example.

4 FIG. 400 1 1 1 1 In the example shown in, in more detail, the compensation selection circuitmay be implemented as a first transistor M. A gate of the first transistor Mis coupled to the compensation selection control terminal OE to receive the compensation selection control signal, a first electrode of the first transistor Mis coupled to the shift signal output terminal CR (not shown for simplicity) to receive the composite output signal, and a second electrode of the first transistor Mis coupled to the control node H to charge the control node H.

4 FIG. 4 FIG. 110 100 2 2 2 1 2 2 10 1 10 10 th th As shown in, the charging sub-circuitin the blanking input circuitmay be implemented as a second transistor M, a gate of the second transistor Mis coupled to the second clock signal terminal CLKB to receive the second clock signal, a first electrode of the second transistor Mis coupled to the blanking input signal terminal STUto receive the blanking input signal, and a second electrode of the second transistor Mis coupled to the control node H. For example, when the second clock signal is a high-level turn-on signal, the second transistor Mis turned on under the control of the second clock signal, so that the blanking input signal may be input to the control node H to charge the control node H. For example, when the shift register unitsshown inare cascaded to form a gate driving circuit, the blanking input signal terminal STUof the shift register unitof the (n+1)stage may be electrically coupled to the shift signal output terminal CR of the shift register unitof the nstage, where n is an integer greater than 0.

4 FIG. 120 100 1 1 1 1 1 110 1 As shown in, the storage sub-circuitin the blanking input circuitmay be implemented as a first capacitor C, a first electrode of the first capacitor Cis coupled to the control node H, and a second electrode of the first capacitor Cis coupled to the first voltage terminal VGLto receive the first voltage. The potential of the control node H can be maintained by providing the first capacitor C, for example, in the display period of the frame, the charging sub-circuitcharges the control node H to a high level, and the first capacitor Ccan maintain the high level of the control node H up to the blanking period of the frame.

4 FIG. 130 100 3 4 3 3 3 4 4 4 3 4 3 4 As shown in, the isolation sub-circuitin the blanking input circuitmay be implemented as a third transistor Mand a fourth transistor M, a gate of the third transistor Mis coupled to the control node H, a first electrode of the third transistor Mis couple to the third clock signal terminal CLKC to receive the third clock signal as the blanking signal, a second electrode of the third transistor Mis coupled to a first electrode of the fourth transistor M, a gate of the fourth transistor Mis coupled to the first clock signal terminal CLKA to receive the first clock signal, and a second electrode of the fourth transistor Mis coupled to the first node Q. For example, in the blanking period of the frame, the third transistor Mis turned on under the control of the control node H, and when the first clock signal is a turn-on signal at a high-level, the fourth transistor Mis turned on under the control of the first clock signal, so that the third clock signal can charge the first node Q through the third transistor Mand the fourth transistor M.

4 FIG. 4 FIG. 200 5 5 2 5 5 5 10 2 10 10 th th th As shown in, the display input circuitmay be implemented as a fifth transistor M, a gate of the fifth transistor Mis coupled to the display input signal terminal STUto receive the display input signal, a first electrode of the fifth transistor Mis coupled to the second voltage terminal VDD to receive the second voltage as the display signal, and a second electrode of the fifth transistor Mis coupled to the first node Q. For example, in the display period of the frame, the fifth transistor Mis turned on under the control of the display input signal, thereby charging the first node Q with the second voltage. For example, when the shift register unitsshown inare cascaded to form a gate driving circuit, the display input signal terminal STUof the shift register unitof the (n+2)stage may be electrically coupled to the shift signal output terminal CR of the shift register unitof the (n+1)stage or the nstage, where n is an integer greater than 0.

4 FIG. 300 6 7 6 6 6 7 7 7 2 2 6 6 7 As shown in, the output circuitmay be implemented to include a sixth transistor M, a seventh transistor M, and a second capacitor. A gate of the sixth transistor Mis coupled to the first node Q, a first electrode of the sixth transistor Mis coupled to the fourth clock signal terminal CLKD to receive the fourth clock signal as the composite output signal, and a second electrode of the sixth transistor Mis coupled to the shift signal output terminal CR; a gate of the seventh transistor Mis coupled to the first node Q, a first electrode of the seventh transistor Mis coupled to the fourth clock signal terminal CLKD to receive the fourth clock signal as the composite output signal, and a second electrode of the seventh transistor Mis coupled to the pixel signal output terminal OUT; a first electrode of the second capacitor Cis coupled to the first node Q, and a second electrode of the second capacitor Cis coupled to the second electrode of the sixth transistor M. For example, when the potential of the first node Q is at a high level, the sixth transistor Mand the seventh transistor Mare turned on, so that the fourth clock signal can be output to the shift signal output terminal CR and the pixel signal output terminal OUT as the composite output signal.

4 FIG. 600 8 9 10 8 8 9 9 10 10 10 1 As shown in, the first control circuitmay be implemented to include an eighth transistor M, a ninth transistor M, and a tenth transistor M, A gate and a first electrode of the eighth transistor Mare coupled together and configured to be coupled to the fourth voltage terminal VDD_A to receive the fourth voltage, and a second electrode of the eighth transistor Mis coupled to the second node QB; a gate and a first electrode of the ninth transistor Mare coupled together and configured to be coupled to the fifth voltage terminal VDD_B to receive the fifth voltage, and a second electrode of the ninth transistor Mis coupled to the second node QB; a gate of the tenth transistor Mis coupled to the first node Q, a first electrode of the tenth transistor Mis coupled to the second node QB, and a second electrode of the tenth transistor Mis configured to be coupled to the first voltage terminal VGLto receive the first voltage.

8 9 8 9 10 10 8 9 10 8 9 11 12 13 For example, the fourth voltage terminal VDD_A and the fifth voltage terminal VDD_B may be configured to be alternately input with a high level, that is, when the fourth voltage terminal VDD_A is input with the high level, the fifth voltage terminal VDD_B is input with a low level, and when the fourth voltage terminal VDD_A is input with the low level, the fifth voltage terminal VDD_B is input with the high level, that is, only one of the eighth transistor Mand the ninth transistor Mis in a turned-on state, so that performance drift caused by long-term turn-on of the transistors may be prevented. When the eighth transistor Mor the ninth transistor Mis turned on, the second node QB may be charged by the fourth voltage or the fifth voltage, thereby pulling the potential of the second node QB to the high level. When the potential of the first node Q is at the high level, the tenth transistor Mis turned on, for example, in terms of transistor design, the tenth transistor Mand the eighth transistor M(or the ninth transistor M) may be configured (for example, configured for size ratio, threshold voltage, and the like of the two transistor) such that when both the tenth transistor Mand the eighth transistor M(or the ninth transistor M) are turned on, the level of the second node QB may be pulled down to the low level, which may keep an eleventh transistor M, a twelfth transistor M, and a thirteenth transistor Mbeing turned off.

4 FIG. 500 11 12 13 11 11 11 1 12 12 12 1 13 13 13 2 2 As shown in, the pull-down circuitmay be implemented to include the eleventh transistor M, the twelfth transistor M, and the thirteenth transistor M. A gate of the eleventh transistor Mis coupled to the second node QB, a first electrode of the eleventh transistor Mis coupled to the first node Q, and a second electrode of the eleventh transistor Mis coupled to the first voltage terminal VGLto receive the first voltage; a gate of the twelfth transistor Mis coupled to the second node QB, a first electrode of the twelfth transistor Mis coupled to the shift signal output terminal CR, and a second electrode of the twelfth transistor Mis coupled to the first voltage terminal VGLto receive the first voltage; a gate of the thirteenth transistor Mis coupled to the second node QB, the first electrode of the thirteenth transistor Mis coupled to the pixel signal output terminal OUT, and a second electrode of the thirteenth transistor Mis coupled to the third voltage terminal VGLto receive the third voltage. It should be noted that, in the embodiments of the present disclosure, for example, the third voltage terminal VGLis configured to input a DC low level signal, that is, the third voltage is at the low level, and the following embodiments are the same and are not described again.

11 12 1 13 2 For example, when the potential of the second node QB is at the high level, the eleventh transistor Mand the twelfth transistor Mare turned on, so that the first node Q and the shift signal output terminal CR may be pulled down by the first voltage terminal VGLto reduce noise of the first node Q and the shift signal output terminal CR. Meanwhile, when the potential of the second node QB is at the high level, the thirteenth transistor Mis also turned on, so that the pixel signal output terminal OUT can be pulled down by the third voltage terminal VGLto reduce noise of the pixel signal output terminal OUT.

2 13 1 It should be noted that, in one example, the first voltage and the third voltage may be different, for example, the first voltage is set to −10V, and the third voltage is set to −6V; in another example, the third voltage terminal VGLmay not be provided, and the second electrode of the thirteenth transistor Mis coupled to the first voltage terminal VGLto receive the first voltage, which is not limited in the embodiments of the present disclosure.

4 FIG. 700 14 14 14 14 1 14 1 100 As shown in, the second control circuitmay be implemented as a fourteenth transistor M. A gate of the fourteenth transistor Mis coupled to the first clock signal terminal CLKA to receive the first clock signal, a first electrode of the fourteenth transistor Mis coupled to the second node QB, and a second electrode of the fourteenth transistor Mis coupled to the first voltage terminal VGLto receive the first voltage. For example, when the first clock signal is at the high level, the fourteenth transistor Mis turned on, so that the second node QB can be pulled down by the first voltage terminal VGL. In this way, the influence of the second node QB on the first node Q can be reduced in the blanking period of the frame, so that the first node Q is charged more sufficiently by the blanking input circuit.

4 FIG. 4 FIG. 800 15 15 2 15 15 1 15 1 10 2 10 10 200 th th th As shown in, the third control circuitmay be implemented as a fifteenth transistor M. A gate of the fifteenth transistor Mis coupled to the display input signal terminal STUto receive the display input signal, a first electrode of the fifteenth transistor Mis coupled to the second node QB, and a second electrode of the fifteenth transistor Mis coupled to the first voltage terminal VGLto receive the first voltage. For example, when the display input signal is at the high level, the fifteenth transistor Mis turned on, so that the second node QB can be pulled down by the first voltage terminal VGL. For example, when the shift register unitsshown inare cascaded to form a gate driving circuit, the display input signal terminal STUof the shift register unitof the (n+2)stage may be electrically coupled to the shift signal output terminal CR of the shift register unitof the (n+1)stage or the nstage, where n is an integer greater than 0. In this way, the influence of the second node QB on the first node Q can be reduced in the display period of the frame, so that the charging of the first node Q by the display input circuitis more sufficient.

4 FIG. 900 16 16 16 16 1 16 1 As shown in, the blanking reset circuitmay be implemented as a sixteenth transistor M. A gate of the sixteenth transistor Mis coupled to the second clock signal terminal CLKB to receive the second clock signal as the blanking reset signal, a first electrode of the sixteenth transistor Mis coupled to the first node Q, and a second electrode of the sixteenth transistor Mis coupled to the first voltage terminal VGLto receive the first voltage. For example, when the second clock signal is at the high level, the sixteenth transistor Mis turned on, so that the first node Q may be reset by using the first voltage terminal VGL.

4 FIG. 4 FIG. 1000 17 17 17 17 1 17 1 10 10 10 th As shown in, the display reset circuitmay be implemented as a seventeenth transistor M. A gate of the seventeenth transistor Mis coupled to the display reset signal terminal STD to receive the display reset signal, a first electrode of the seventeenth transistor Mis coupled to the first node Q, and a second electrode of the seventeenth transistor Mis coupled to the first voltage terminal VGLto receive the first voltage. For example, when the display reset signal is at the high level, the seventeenth transistor Mis turned on, so that the first node Q may be reset by using the first voltage terminal VGL. For example, when the shift register unitsshown inare cascaded to form a gate driving circuit, the display reset signal terminal STD of the shift register unitof the nstage may be coupled to the shift signal output terminal CR of the shift register unitof a next stage.

5 FIG. 4 FIG. 5 FIG. 10 10 300 10 18 500 19 As shown in, another embodiment of the present disclosure further provides a shift register unit, and compared with the shift register unitshown in, the output circuitof the shift register unitshown inmay further include an eighteenth transistor M, and correspondingly, the noise reduction circuitmay further include a nineteenth transistor M.

5 FIG. 18 18 18 2 18 2 2 As shown in, a gate of the eighteenth transistor Mis coupled to the first node Q, a first electrode of the eighteenth transistor Mis coupled to a fifth clock signal terminal CLKE to receive a fifth clock signal, and a second electrode of the eighteenth transistor Mis coupled to another pixel signal output terminal OUT. For example, when the potential of the first node Q is at the high level, the eighteenth transistor Mis turned on, thereby outputting the fifth clock signal to the pixel signal output terminal OUT. For example, in one example, the fifth clock signal input by the fifth clock signal terminal CLKE may be configured to be the same as the fourth clock signal input by the fourth clock signal terminal CLKD; for another example, in another example, the fifth clock signal may be different from the fourth clock signal, so that the pixel signal output terminals OUT and OUTmay output different signals, respectively, to improve the driving capability.

5 FIG. 19 19 2 19 2 19 2 2 As shown in, a gate of the nineteenth transistor Mis coupled to the second node QB, a first electrode of the nineteenth transistor Mis coupled to the pixel signal output terminal OUT, and a second electrode of the nineteenth transistor Mis coupled to the third voltage terminal VGL. For example, when the potential of the second node QB is at the high level, the nineteenth transistor Mis turned on, so that noise reduction of the pixel signal output terminal OUTcan be performed using the third voltage terminal VGL.

Although only the examples of the shift register unit including two and three output terminals are shown above, it can be understood by those skilled in the art that more output terminals may be provided according to the practical situation according to the description of the present disclosure, and the above examples should not be construed as limiting the scope of the present disclosure.

10 1 2 1 2 1 2 1 2 1 2 4 11 16 17 10 As described above, in the shift register unitprovided in the embodiments of the present disclosure, the potential at the control node H may be maintained by the first capacitor C, and the potential at the first node Q may be maintained by the second capacitor C. The first capacitor Cand/or the second capacitor Cmay be implemented by a capacitor device manufactured by a process, for example, by manufacturing dedicated capacitor electrodes, each electrode of the capacitor may be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), or the like, or the first capacitor Cand/or the second capacitor Cmay be implemented by a parasitic capacitor between the devices. The connection mode of the first capacitor Cand/or the second capacitor Cis not limited to the above-described mode, and other suitable connection modes may be used as long as the level written into the control node H or the first node Q can be stored. When the potential of the first node Q and/or the control node H are maintained at the high level, there are some transistors (e.g., the first transistor M, the second transistor M, the fourth transistor M, the eleventh transistor M, the sixteenth transistor M, and the seventeenth transistor M) of which first electrodes are coupled to the first node Q and/or the control node H and of which second electrodes each are coupled to a low-level signal terminal. Even when a non-turn-on signal is input to the gates of these transistors, a leakage may occur due to a voltage difference between the first and second electrodes thereof, thereby deteriorating the effect of maintaining the potential of the first node Q and/or the control node H in the shift register unit.

4 FIG. 2 1 2 1 2 For example, as shown in, taking the control node H as an example, the first electrode of the second transistor Mis coupled to the blanking input signal terminal STUand the second electrode of the second transistor Mis coupled to the control node H. When the control node H is at the high level and the signal input from the blanking input signal terminal STUis at the low level, current leakage through the second transistor Mmay occur at the control node H.

6 FIG. 4 FIG. 10 10 10 1 2 4 11 16 17 20 21 2 In view of the above problem, as shown in, a shift register unitcapable of preventing current leakage is provided in an embodiment of the present disclosure. The shift register unitis different from the shift register unitinin that a first leakage prevention transistor M_b, a second leakage prevention transistor M_b, a fourth leakage prevention transistor M_b, an eleventh leakage prevention transistor M_b, a sixteenth leakage prevention transistor M_b, a seventeenth leakage prevention transistor M_b, a twentieth transistor Mand a twenty-first transistor Mare added. The operation principle of the leakage prevention will be described below by taking the second leakage prevention transistor M_b as an example.

2 2 20 2 20 20 20 2 2 2 2 2 2 2 2 A gate of the second leakage prevention transistor M_b is coupled to the second clock signal terminal CLKB, a first electrode of the second leakage prevention transistor M_b is coupled to a second electrode of the twentieth transistor M, and a second electrode of the second leakage prevention transistor M_b is coupled to the control node H. A gate of the twentieth transistor Mis coupled to the control node H, and a first electrode of the twentieth transistor Mis coupled to the second voltage terminal VDD to receive the second voltage at the high level. When the control node H is at the high level, the twentieth transistor Mis turned on under the control of the level of the control node H, so that a high level signal input from the second voltage terminal VDD can be input to the first electrode of the second leakage prevention transistor M_b, thereby causing both the first electrode and the second electrode of the second leakage prevention transistor M_b to be in the high level state, preventing the charges at the control node H from leaking through the second leakage prevention transistor M_b. At this time, since the gate of the second leakage prevention transistor M_b is coupled to the gate of the second transistor M, combination of the second transistor Mand the second leakage prevention transistor M_b can achieve the same effect as the aforementioned second transistor Mwhile having a leakage preventing effect.

1 20 1 1 4 11 16 17 21 Similarly, the first leakage prevention transistor M_b in combination with the twentieth transistor Mmay prevent the charges at the control node H from leaking through the first leakage prevention transistor M_b and the first transistor M. Similarly, the fourth leakage prevention transistor M_b, the eleventh leakage prevention transistor M_b, the sixteenth leakage prevention transistor M_b, and the seventeenth leakage prevention transistor M_b may implement a leakage prevention structure in combination with the twenty-first transistor M, respectively, so that the leakage of the charge at the first node Q may be prevented. The working principle of preventing the first node Q from leaking is the same as the working principle of preventing the control node H from leaking, and the detailed description is omitted here.

It should be noted that all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and all the embodiments of the present disclosure are described by taking thin film transistors as examples. The source and the drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and the drain. In the embodiments of the present disclosure, in order to distinguish two electrodes of a transistor except for the gate, one of them is directly described as the first electrode, and the other is the second electrode. Further, the transistors may be classified into N-type and P-type transistors according to their characteristics. In a case where the transistor is a P-type transistor, the turn-on voltage is a low level voltage (e.g., 0V, −5V, −10V or other suitable voltage), and the turn-off voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage); in a case where the transistor is an N-type transistor, the turn-on voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage) and the turn-off voltage is a low level voltage (e.g., 0V, −5V, −10V, or other suitable voltage).

10 10 In addition, it should be noted that the transistors used in the shift register unitprovided in the embodiments of the present disclosure are all illustrated by taking N-type transistors as examples, the embodiments of the present disclosure include but are not limited to this, for example, at least some of the transistors in the shift register unitmay also be P-type transistors.

20 20 10 10 10 20 7 FIG. 7 FIG. An embodiment of the present disclosure provides a gate driving circuit, as shown in, the gate driving circuitincludes a plurality of shift register unitswhich are cascaded, where any one or more shift register unitsmay adopt the structure of the shift register unitprovided in the embodiments of the present disclosure or a variation thereof. Note that only the front four stages of shift register units (A1, A2, A3, and A4) of the gate driving circuitare schematically shown in.

7 FIG. 20 1 2 3 4 1 2 3 4 th th th th As shown in, the gate driving circuitfurther includes a first sub-clock signal line CLK_, a second sub-clock signal line CLK_, a third sub-clock signal line CLK_, and a fourth sub-clock signal line CLK_. In a case where the shift register unit includes the fourth clock signal terminal CLK_D, the fourth clock signal terminal CLKD of the shift register unit of the (4n-3)stage is coupled to the first sub-clock signal line CLK_; the fourth clock signal terminal CLKD of the shift register unit of the (4n-2)stage is coupled to the second sub-clock signal line CLK_; the fourth clock signal terminal CLKD of the shift register unit of the (4n-1)stage is coupled to the third sub-clock signal line CLK_; the fourth clock signal terminal CLKD of the shift register unit of the (4n)stage is coupled to the fourth sub-clock signal line CLK_, where n is an integer greater than 0.

7 FIG. 20 5 6 5 6 6 5 th th As shown in, the gate driving circuitmay further include a fifth sub-clock signal line CLK_and a sixth sub-clock signal line CLK_. In a case where the shift register unit includes the second clock signal terminal CLKB and the third clock signal terminal CLKC, the second clock signal terminal CLKB of the shift register unit of the (2n-1)stage is coupled to the fifth sub-clock signal line CLK_, and the third clock signal terminal CLKC is coupled to the sixth sub-clock signal line CLK_; the second clock signal terminal CLKB of the shift register unit of the (2n)stage is coupled to the sixth sub-clock signal line CLK_, the third clock signal terminal CLKC is coupled to the fifth sub-clock signal line CLK_, where n is an integer greater than 0.

7 FIG. 20 7 7 As shown in, the gate driving circuitmay further include a seventh sub-clock signal line CLK_, and the first clock signal terminal CLKA of each stage of the shift register unit is coupled to the seventh sub-clock signal line CLK_.

7 FIG. 1 2 2 1 2 th th th th th th As shown in, the blanking input signal terminal STUand the display input signal terminal STUof the shift register unit of the first stage, and the display input signal terminal STUof the shift register unit of the second stage are coupled to the input signal line STU, for example, to receive a trigger signal STV. The blanking input signal terminal STUof the shift register unit of the (n+1)stage, except for the shift register unit of the first stage, is coupled with the shift signal output terminal CR of the shift register unit of the nstage. The display input signal terminal STUof the shift register unit of the (n+2)stage, except for the shift register units of the first and second stages, is coupled to the shift signal output terminal CR of the shift register unit of the nstage. The display reset signal terminal STD of the shift register unit of the nstage, except for the shift register units of the last three stages, is coupled to the shift signal output terminal CR of the shift register unit of the (n+3)stage, where n is an integer greater than 0.

8 FIG. 7 FIG. 9 FIG. 7 FIG. 8 9 FIGS.and 8 9 FIGS.and 20 20 1 2 20 1 2 3 4 20 1 2 3 4 shows a signal timing chart illustrating signals of the gate driving circuitshown inwhen used for the progressive sequential compensation, andshows a signal timing chart illustrating signals of the gate driving circuitshown inwhen used for the random compensation. In, Q<> and Q<> respectively denote the first nodes Q in the shift register units of the first stage and the second stage in the gate driving circuit. OUT<>, OUT<>, OUT<>, and OUT<> respectively denote pixel signal output terminals OUT of the shift register units of the first stage, the second stage, the third stage, and the fourth stage in the gate driving circuit.F,F,F, andF denote a first frame, a second frame, a third frame, and a fourth frame, respectively. Display denotes a display period of the frame, and Blank denotes a blanking period of the frame. It should be noted that, since the shift signal output terminal CR and the pixel signal output terminal OUT in each stage of the shift register unit have a same potential, the shift signal output terminal CR is not shown in.

8 9 FIGS.and It should be noted that the signal levels in the signal timing charts shown inare only schematic and do not represent the true level values.

20 20 7 FIG. 8 FIG. 4 FIG. 7 FIG. The operation principle of the gate driving circuitshown inwhen used for the progressive sequential compensation is explained below with reference to the signal timing diagram in, for example, the shift register unit shown incan be used as the shift register unit in the gate driving circuitshown in.

1 1 5 6 5 6 2 16 6 5 When the progressive sequential compensation is performed, a DC low-level signal is input through the compensation selection control terminal OE, so that the first transistor Mremains turned off. Before the first frameF starts, the fifth and sixth sub-clock signal lines CLK_and CLK_are supplied with a high level, and since the fifth and sixth sub-clock signal lines CLK_and CLK_are alternately coupled to the second clock signal terminal CLKB of the shift register unit, the second transistor Mand the sixteenth transistor Mof the shift register unit of each stage may be turned on, and thus the control node H and the first node Q of the shift register unit of each stage may be reset to implement global reset. Then, the signal supplied from the sixth sub-clock signal line CLK_becomes a low level, and the signal supplied from the fifth sub-clock signal line CLK_continues to remain the high level.

9 11 Since a high level is input from the fifth voltage terminal VDD_B, the ninth transistor Mis turned on, so that the second node QB is charged to the high level. The high level of the second node QB turns on the eleventh transistor M, thereby pulling down the first node Q to the low level.

1 In the display period Display of the first frameF, the operation of the shift register unit of the first stage is described as follows.

1 1 2 1 2 5 2 1 15 2 In a first stage, the blanking input signal terminal STUand the display input signal terminal STUof the shift register unit of the first stage are both coupled to the input signal line STU, so that the blanking input signal terminal STUand the display input signal terminal STUare both initially input with a high level, and at the same time, since the second clock signal terminal CLKB (coupled to the fifth sub-clock signal line CLK_) is input with a high level, the second transistor Mis turned on, and the control node H is charged to a high level, which is then stored by the first capacitor C. The fifteenth transistor Mis turned on by the high level of the display input signal terminal STU, so that the second node QB may be secondarily pulled down.

2 2 5 2 6 7 1 Then, the second clock signal terminal CLKB is input with a low level, the second transistor Mis turned off, and the display input signal terminal STUcontinues to be input with the high level, so that the high level signal of the second voltage terminal VDD can charge the first node Q through the fifth transistor M, and the first node Q is pulled up to the high level, which is then stored by the second capacitor C. The sixth transistor Mand the seventh transistor Mare turned on under the control of the first node Q, but since the fourth clock signal terminal CLKD (coupled to the first sub-clock signal line CLK_) is input with a low level signal at this time, both the shift signal output terminal CR and the pixel signal output terminal OUT each output a low level signal.

2 6 7 In a second stage, the fourth clock signal terminal CLKD is input with a high level signal, the potential of the first node Q is further pulled up due to the bootstrap effect, so the sixth transistor Mand the seventh transistor Mremain turned on, and thus both the shift signal output terminal CR and the pixel signal output terminal OUT each output a high level signal. For example, the high level signal output from the shift signal output terminal CR may be used for scan shift from a shift register unit of a previous stage to that of a next stage, and the high level signal output from the pixel signal output terminal OUT may be used for driving the sub-pixel units in the display panel to perform display.

3 In a third stage, a low level signal is then input to the fourth clock signal terminal CLKD, and both the shift signal output terminal CR and the pixel signal output terminal OUT can be discharged through the fourth clock signal terminal CLKD, thereby completing the reset of the shift signal output terminal CR and the pixel signal output terminal OUT. Since the shift signal output terminal CR and the pixel signal output terminal OUT are reset to the low level, the potential of the first node Q is lowered by an amplitude with the coupling action between the transistors; meanwhile, the display reset signal terminal STD of the shift register unit of the first stage is coupled with the shift signal output terminal CR of the shift register unit of the fourth stage, and at this time, the shift signal output terminal CR of the shift register unit of the fourth stage does not output a high level signal, so that the first node Q is not pulled down, and the first node Q can be kept at a relatively high level.

4 17 In a fourth stage, the shift signal output terminal CR of the shift register unit of the fourth stage then outputs a high level, so that the display reset signal terminal STD of the shift register unit of the first stage is input with a high level signal, the seventeenth transistor Mis turned on, and the first node Q is pulled down to the low level, completing the reset of the first node Q.

6 7 6 7 12 13 By the above process, the potential change of the first node Q of the first stage takes on a “tower shape”. When the shift signal output terminal CR and the pixel signal output terminal OUT are at the high level, the potential of the first node Q rises due to the bootstrap effect, so that when the shift signal output terminal CR and the pixel signal output terminal OUT are discharged through the sixth transistor Mand the seventh transistor M, respectively, the current flowing through the transistors may be greater, and the discharge speed is faster. Meanwhile, since the charges accumulated at the shift signal output terminal CR and the pixel signal output terminal OUT can be discharged through the sixth transistor Mand the seventh transistor M, respectively, the twelfth transistor Mand the thirteenth transistor Mfor resetting can be transistors with smaller sizes, so that the layout area occupied by the shift register unit can be reduced.

7 4 4 In the display period of the above-described first frame, since the first clock signal terminal CLKA (coupled to the seventh sub-clock signal line CLK_) is always kept at the low level, the fourth transistor Mis kept in the off state, and the fourth transistor Misolates the influence of the high level pre-stored at the control node H on the display period.

After the shift register unit of the first stage drives the sub-pixels in the first row in the display panel to complete display, the shift register unit of the second stage, the shift register unit of the third stage and the like drive the sub-pixel units in the display panel row by row to complete display driving of the frame. To this end, the display period of the first frame ends.

1 In the blanking period Blank of the first frameF, the operation process of the shift register unit of the first stage is described below.

5 1 7 6 3 4 10 14 In a fifth stage, the control node H maintains the high level of the display period due to the storage of the first capacitor C, the first clock signal terminal CLKA (coupled to the seventh sub-clock signal line CLK_) and the third clock signal terminal CLKC (coupled to the sixth sub-clock signal line CLK_) are input with the high level signal at the beginning, the third transistor Mand the fourth transistor Mare turned on, so that the high level of the third clock signal terminal CLKC may charge the first node Q, pulling the first node Q up to the high level. The tenth transistor Mis turned on under the control of the first node Q, the second node QB is pulled down to the low level, and the fourteenth transistor Mis also turned on under the control of the first clock signal terminal CLKA, which may further pull down the second node QB.

6 4 1 6 7 In a sixth stage, the first clock signal terminal CLKA is input with a low level signal, and the fourth transistor Mis turned off. The fourth clock signal terminal CLKD (coupled to the first sub-clock signal line CLK_) is input with a high level signal, the potential of the first node Q is further pulled up due to the bootstrap effect, the sixth transistor Mand the seventh transistor Mare turned on, and the high level signal input from the fourth clock signal terminal CLKD may be output to the shift signal output terminal CR and the pixel signal output terminal OUT. For example, the signal output by the pixel signal output terminal OUT can be used to drive a sensing transistor in a sub-pixel unit in the display panel to achieve external compensation.

6 1 2 2 Meanwhile, since the second clock signal terminal CLKB of the shift register unit of the second stage is coupled to the sixth sub-clock signal line CLK_and the blanking input signal terminal STUof the shift register unit of the second stage is coupled to the shift signal output terminal CR of the shift register unit of the first stage, the second transistor Min the shift register unit of the second stage is turned on, so that the control node H<> in the shift register unit of the second stage is pulled up to a high level.

7 2 6 4 1 4 In a seventh stage, after the control node H<> in the shift register unit of the second stage is sufficiently written with the high level, the sixth sub-clock signal line CLK_is input with the low level signal. Meanwhile, the fourth clock signal terminal CLKD is continuously input with the high level, so the shift signal output terminal CR and the pixel signal output terminal OUT of the shift register unit of the first stage keep outputting the high level signal. In this process, the fourth transistor Mis kept in the off state all the time, so that the first node Q<> can be prevented from leaking through the fourth transistor M.

8 5 5 In an eighth stage, that is, in a last stage of the blanking period, the fifth sub-clock signal line CLK_is input with a high level signal, and since the second clock signal terminals CLKB of the shift register units of the odd-numbered stages are all coupled to the fifth sub-clock signal line CLK_, the reset of the control nodes H and the first nodes Q in all the shift register units of the odd-numbered stages, particularly the reset of the first nodes Q of the first and third stages and the control node H of the first stage, can be completed. Since the threshold voltage of the transistor may be positively drifted when a positive voltage is applied to the transistor, the time for which the control node H needs to be kept at the positive voltage can be shortened by the above manner, so that the time for the threshold voltage of the transistor to be positively drifted is shortened, and the reliability of the transistor is improved.

At this point, the driving timing of the first frame ends.

20 In the display period of the second frame, the gate driving circuitrepeats the same operation as the display period of the first frame, and is not described here again.

5 3 4 2 6 6 In the blanking period of the second frame, for the shift register unit of the second stage, since the third clock signal terminal CLKC is coupled to the fifth sub-clock signal line CLK_, at the beginning of the blanking period, the first clock signal terminal CLKA and the third clock signal terminal CLKC of the shift register unit of the second stage each are input with a high level signal, and the third transistor Mand the fourth transistor Mare turned on, so that the high level input by the third clock signal terminal CLKC can charge the first node Q, pulling up the first node Q to a high level. Then, when a high level signal is input to the second sub-clock signal line CLK_, the shift signal output terminal CR and the pixel signal output terminal OUT output high level signals while charging the control node H in the shift register unit of the third stage. At the last stage of the blanking period of the second frame, a high level signal is input by the sixth sub-clock signal line CLK_, and since the second clock signal terminals CLKB of the shift register units of the even-numbered stages are all coupled to the sixth sub-clock signal line CLK_, the reset of the control nodes H and the first nodes Q in all the shift register units of the even-numbered stages can be completed.

At this point, the driving timing of the second frame ends. For the subsequent driving of the gate driving circuit in more stages in the third frame, the fourth frame, the fifth frame and the like, reference may be made to the above description, and details are not repeated here.

As described above, the gate driving circuit outputs the driving signals for the sensing transistors in the sub-pixel units in the display panel in the blanking period of each frame, and the driving signals are sequentially supplied row by row. For example, in the blanking period of the first frame, the gate driving circuit outputs the driving signal for the sub-pixel units of the first row in the display panel, in the blanking period of the second frame, the gate driving circuit outputs the driving signal for the sub-pixel units of the second row in the display panel, and so on, the progressive sequential compensation is completed.

20 20 7 FIG. 9 FIG. 4 FIG. 7 FIG. The operation principle of the gate driving circuitshown inwhen used for random compensation is described below with reference to the signal timing diagram in, for example, the shift register unit shown inmay be used as the shift register unit in the gate driving circuitshown in.

9 FIG. 1 1 2 1 2 In the display period of the first frame, the operation principle of the gate driving circuit is similar to that in the above-described progressive sequential compensation, and only the difference is described below. As shown in, when the pixel signal output terminal OUT<> (i.e., the shift signal output terminal CR) of the shift register unit of the first stage outputs a high level signal, the compensation selection control terminal OE is also supplied with a high level signal, at which time the control node H<> of the shift register unit of the first stage is charged to a high level, and then the control node H<> of the shift register unit of the second stage is also charged to a high level because the output pulses of OUT<> and OUT<> overlap.

1 2 As can be seen from the above, in the display period of the first frame, the control node H<> of the shift register unit of the first stage and the control node H<> of the shift register unit of the second stage are both charged to the high level, but in the blanking period of the first frame, for example, when it is necessary to output a driving signal for detecting the first row of sub-pixel units in the display panel in the frame, the following operation is performed in the blanking period of the first frame.

1 6 2 th th th In a first stage T, a high level signal is input by the sixth sub-clock signal line CLK_, thereby discharging the control nodes H of shift register units of the even-numbered stages, that is, eliminating the high level of H<> (for example, eliminating the high levels of the control nodes H of the shift register units of the (n−1)and the (n+1)stages, if the shift register unit of the nstage needs to be detected in the frame).

2 7 3 4 In a second stage T, the seventh sub-clock signal line CLK_(coupled to the first clock signal terminal CLKA) is input with a high level signal, the third clock signal terminal CLKC of the shift register unit of the first stage maintains to be input with the high level signal, the third transistor Mand the fourth transistor Mare turned on, and the charging of the first node Q is completed.

3 6 7 1 1 In a third stage T, low-level signals are input by the sixth and seventh sub-clock signal lines CLK_and CLK_, and a high level signal is input by the first sub-clock signal line CLK_, so the shift signal output terminal and the pixel signal output terminal OUT output high level signals. For example, the signal output by the pixel signal output terminal OUT can be used to drive the sensing transistor in the sub-pixel units of the first row in the display panel for external compensation. Then, the signal of the first sub-clock signal line CLK_becomes a low level signal, and accordingly, the shift signal output terminal and the pixel signal output terminal OUT output low level signals.

4 5 5 In a fourth stage T, that is, in the last stage of the blanking period of the first frame, a high level signal is input by the fifth sub-clock signal line CLK_, and since the second clock signal terminals CKLB of the shift register units of the odd-numbered stages are all coupled to the fifth sub-clock signal line CLK_, the reset of the control nodes H and the first nodes Q in all the shift register units of the odd-numbered stages, and particularly the reset of the first node Q and the control node H of the shift register unit of the first stage, can be completed.

For example, when a driving signal for detecting the second row of sub-pixel units in the display panel needs to be output in the blanking period of the second frame, the following operation is performed in the second frame.

2 1 2 3 2 1 3 1 1 1 9 FIG. In the display period of the second frame, the signal input by the compensation selection control terminal OE is made to be the same as the signal outputted by the pixel signal output terminal OUT<> (i.e., the shift signal output terminal CR) of the shift register unit of the second stage, and the control nodes H<>, H<> and H<> of the shift register units of the first stage, the second stage and the third stage are all charged to a high level under the control of the compensation selection control terminal OE due to the overlap of output pulses of the pixel signal output terminals OUT<>, OUT<> and OUT<> (not shown in) of the shift register units of the first to third stages. Since the first electrode of the first transistor Mof the shift register unit of the first stage is coupled to the shift signal output terminal CR of the shift register unit of the first stage, the control node H<> is charged to the high level and then pulled down fast by the low level of the shift signal output terminal CR (i.e., the pixel signal output terminal OUT<>).

For the operation principle in the blanking period of the second frame, reference may be made to the corresponding description in the blanking period of the first frame, which is not described here in detail.

11 FIG. 11 FIG. 5 4 6 It should be noted that, in order to more conveniently illustrate the signal timing, when the above description is made on the operation principle of the random compensation, the description is given by taking as an example that the driving signal corresponding to the first row of the sub-pixel units of the display panel is output in the blanking period of the first frame, and the disclosure is not limited thereto. For example, as in the timing simulation diagram shown in, when it is necessary to output a driving signal corresponding to the fifth row of sub-pixel units of the display panel in the blanking period of a certain frame, it is necessary to control so that the timings of the signals supplied to the compensation selection control terminal OE and the signal output terminal CR<> of the shift register unit of the fifth stage are the same. It should be noted here that the two signals having the same timing refers to that the two signals are at a high level synchronously, and the two signals are not required to have the same amplitude. CR<> and CR<> indenote a shift signal output terminal of the shift register unit of the fourth stage and a shift signal output terminal of the shift register unit of the sixth stage, respectively.

400 1 th th As described above, by providing the compensation selection circuit(the first transistor M), when it is necessary to output the driving signal corresponding to the sub-pixel units of the nrow of the display panel in the blanking period of a certain frame, it is necessary to make the signal supplied to the compensation selection control terminal OE and the signal of the shift signal output terminal CR of the shift register unit of the nstage have a same timing, whereby the random compensation can be achieved, where n is an integer greater than 0.

10 FIG. 7 FIG. 10 FIG. 20 20 20 1 2 20 th th th th As shown in, another embodiment of the present disclosure further provides a gate driving circuit, the differences between the present gate driving circuitand the gate driving circuitshown ininclude: the blanking input signal terminal STUand the display input signal terminal STUof the shift register unit of the (n+1)stage, except for the shift register unit of the first stage, are coupled to the shift signal output terminal CR of the shift register unit of the nstage; the display reset signal terminal STD of the shift register unit of the nstage, except for the shift register unit of the last stage, is coupled to the shift signal output terminal CR of the shift register unit of the (n+1)stage. There is no overlap between the signal pulses output by the gate drive circuitshown in.

1 1 20 1 40 410 1 30 30 20 410 30 410 20 410 12 FIG. An embodiment of the present disclosure also provides a display device, as shown in, the display deviceincludes the gate driving circuitprovided by the embodiments of the present disclosure. The display devicefurther includes a display panel, which includes a plurality of sub-pixel unitsin an array. For example, the display devicemay further include a data driving circuit. The data driving circuitis used for supplying data signals to the pixel array. The gate drive circuitis used to provide driving signals to the pixel array, for example, the driving signals may drive scan transistors and sense transistors in the sub-pixel units. The data driving circuitis electrically coupled to the sub-pixel unitsthrough data lines DL, and the gate driving circuitis electrically coupled to the sub-pixel unitsthrough gate lines GL.

1 Note that, the display devicein the present embodiment may be any product or component with a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator and the like.

1 20 Technical effects of the display deviceprovided by the embodiments of the present disclosure can refer to corresponding descriptions about the gate driving circuitin the above embodiments, and are not described herein again.

1300 10 1300 Embodiments of the present disclosure also provide a driving method, which may be used to drive the shift register unitprovided by the embodiments of the present disclosure, where the driving methodincludes the following steps.

1302 200 300 At step S, in a first input stage of a display period of the frame, the display input circuitinputs a display signal to the first node Q in response to a display input signal; in a first output stage of the display period of the frame, the output circuitoutputs a first output signal under the control of the level of the first node Q. For example, the first output signal may be used to drive the sub-pixel units in the display panel to display.

1304 100 300 At step S, in a second input stage of a blanking period of the frame, the blanking input circuitinputs a blanking input signal to the control node H and a blanking signal to the first node Q; in a second output stage of the blanking period of the frame, the output circuitoutputs a second output signal under the control of the level of the first node Q. For example, the second output signal may be used to drive the sub-pixel units in the display panel to perform external compensation. The composite output signal includes a first output signal and a second output signal.

1300 400 In another embodiment, the driving methodmay further include: the compensation selection circuitcharges the control node with the first output signal in response to the compensation selection control signal during the display period of the frame.

1400 20 Embodiments of the present disclosure also provide a driving method, which may be used to drive the gate driving circuitprovided by the embodiments of the present disclosure, and the driving method includes the following steps.

1402 20 10 400 10 10 th th th At step S, when the gate driving circuitdrives a display panel, in a display period of any frame, the output terminal of the shift register unitof the nstage outputs a first output signal, and the compensation selection circuitin the shift register unitof the nstage charges the control node H in the shift register unitof the nstage with the first output signal in response to the compensation selection control signal.

1404 th At step S, in the blanking period of the frame, the output terminal of the shift register unit of the nstage outputs the second output signal. The composite output signal includes a first output signal and the second output signal, where n is an integer greater than 0.

10 20 It should be noted that, for detailed description and technical effects of the driving method provided by the embodiments of the present disclosure, reference may be made to the description of the operation principles of the shift register unitand the gate driving circuitin the embodiments of the present disclosure, and details are not described here.

The above is only specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be determined by the scope of the claims.