Gate driving circuit and display device using the same

This applicationis a reissue of U.S. Pat. No. 10,991,302 issued on Apr. 27, 2021, which was filed as U.S. patent application Ser. No. 16/918,882 on Jul. 1, 2020, whichclaims priority from Republic of Korea Patent Application No. 10-2019-0175347, filed on Dec. 26, 2019, which is hereby incorporated by reference in its entirety.

The present disclosure relates to a gate driving circuit and a display device using the same, and more specifically, to a gate driving circuit and a display device using the same for realizing a display device with a narrow bezel by integrating a first scan signal generator and a second scan signal generator using nodes Q/QB of logic circuits.

Currently, various display devices are being developed and have entered the market. For example, there are display devices such as a liquid crystal display (LCD) device, a field emission display (FED) device, an electrophoretic display (EPD) device, an electrowetting display (EWD) device, an organic light emitting display (OLED) device, and a quantum dot display (QD) device.

In the development of various technologies for realizing display devices and mass production of various products, technical enhancement is achieved on the basis of technology for realizing designs that consumers desire rather than technology for operating display devices. One technology to this end is increasing a display screen size. This is for the purpose of reducing a non-display area surrounding a display screen, that is, a bezel, and increasing the size of a display area to improve the immersiveness of a user for the display screen and diversify product design.

In the bezel, driving circuits for transmitting driving signals to a pixel array constituting the display screen are arranged.

When signals supplied from the driving circuits drive pixel circuits, the pixel array emits light. A gate driving circuit is provided to transmit gate signals to gate lines of pixel circuits. A data driving circuit is provided to transmit data signals to data lines of the pixel circuits. The gate driving circuit may include a scan driving circuit for controlling data electrodes of scan transistors or switching transistors of pixel circuits and an emission driving circuit for controlling gate electrodes of emission switching transistors.

A scan driving circuit of a conventional gate driving circuit uses separate drivers for output of a first scan signal for determining whether a data voltage will be transferred to a driving transistor and a second scan signal for compensating for the driving transistor. The size of a bezel increases because the two scan drivers are provided.

A technology for reducing the bezel by reducing the area in which a gate driving circuit is arranged is required.

The present disclosure is to provide a gate driving circuit and a display device using the same which can realize a narrow bezel.

The present disclosure is to provide a gate driving circuit and a display device using the same which can secure a driving initialization time of a driving transistor.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a gate driving circuit includes a first scan signal generator and a second scan signal generator which are integrated using nodes Q/QB of a logic circuit.

There is provided a gate driving circuit according to the present disclosure which comprises a logic signal generator including a node Q and a node QB outputting a logic signal reverse to a logic signal of the node Q and outputting a carry signal, and a scan signal generator in which a first scan signal generator for generating a first scan signal for applying a data voltage to driving transistors of pixel circuits for an initialization time by sharing the node Q and the node QB of the logic signal generator is integrated with a second scan signal generator for generating a second scan signal representing the same logic voltage signal as the first scan signal for the initialization time and representing a logic voltage signal reverse to the first scan signal for a sampling time by sharing the node Q and the node QB of the logic signal generator.

The gate driving circuit according to the present disclosure may have an initialization time of 4 horizontal periods and a sampling time of 1 horizontal period using 6-phase clock signals.

The gate driving circuit according to the present disclosure may have an initialization time of 6 horizontal periods and a sampling time of 1 horizontal period using 8-phase clock signals.

The gate driving circuit according to the present disclosure may include the logic signal generator including a first transistor having a gate electrode connected to the node Q and a second transistor serially connected to the first transistor and having a gate electrode connected to the node QB and outputting a carry pulse signal through a node shared by the first transistor and the second transistor. The first scan signal generator may include a third transistor having a gate electrode connected to the node Q and a fourth transistor serially connected to the third transistor and having a gate electrode connected to the node QB and output the first scan signal through a node shared by the third transistor and the fourth transistor. And the second scan signal generator may include a fifth transistor having a gate electrode connected to the node Q and a sixth transistor serially connected to the fifth transistor and having a gate electrode connected to the node QB and output the second scan signal through a node shared by the fifth transistor and the sixth transistor.

All transistors in the gate driving circuit according to the present disclosure may be p-type transistors.

In the gate driving circuit according to the present disclosure, a first clock signal may be supplied to one terminal of the first transistor, a second high-level voltage may be supplied to one terminal of the second transistor, a first high-level voltage may be supplied to one terminal of the third transistor, a first low-level voltage may be supplied to one terminal of the fourth transistor, a fourth clock signal may be supplied to one terminal of the fifth transistor, and the second high-level voltage may be supplied to one terminal of the sixth transistor.

In the gate driving circuit according to the present disclosure, a capacitor may be disposed between a connecting point of the node Q and the gate electrode of the fifth transistor and the node shared by the fifth transistor and the sixth transistor.

The first scan signal generator of the gate driving circuit according to the present disclosure may include a first signal transmission transistor having a source electrode connected to the node Q and a drain electrode connected to the gate electrode of the third transistor and turned on all the time by receiving a second low-level voltage through a gate electrode, and the second scan signal generator may include a second signal transmission transistor having a source electrode connected to the node Q and a drain electrode connected to the gate electrode of the fifth transistor and turned on all the time by receiving the second low-level voltage through a gate electrode.

1 5 6 1 2 6 4 1 3 5 6 5 1 4 6 In the gate driving circuit according to the present disclosure, the logic signal generator, the first scan signal generator and the second scan signal generator may output a high-level voltage when first to fifth clock signals CLKto CLKare a low-level voltage and a start pulse signal VST and a sixth clock signal CLKare the low-level voltage, the logic signal generator may output the low-level voltage and the first scan signal generator and the second scan signal generator may output the high-level voltage when the first clock signal CLKis the low-level voltage and the start pulse signal VST and the second to sixth clock signals CLKto CLKare the high-level voltage, the logic signal generator and the first scan signal generator may output the high-level voltage and the second scan signal generator may output the high-level voltage when the fourth clock signal CLKis the low-level voltage and the start pulse signal VST, the first to third clock signals CLKto CLKand the fifth and sixth clock signals CLKand CLKare the high-level voltage, and the logic signal generator and the second scan signal generator may output the high-level voltage and the first scan signal generator may output the low-level voltage when the fifth clock signal CLKis the low-level voltage and the start pulse signal VST, the first to fourth clock signals CLKto CLKand the sixth clock signal CLKare the high-level voltage.

A display device according to the present disclosure comprises a substrate including a display area and a non-display area, pixel circuits each including a driving transistor for transferring current necessary to operate a light-emitting diode according to a switching operation and arranged in the display area, and a gate driving circuit included in the non-display area and including a first scan signal generator and a second scan signal generator which are integrated using nodes Q/QB of a logic circuit.

In the display device according to the present disclosure, each pixel circuit may include at least one oxide semiconductor transistor and at least one polysilicon transistor.

In the display device according to the present invention, each pixel circuit may include a first scan transistor configured to receive a first scan signal and apply the first scan signal to a gate electrode of the driving transistor, and a second scan transistor configured to receive a second scan signal and perform a switching operation for compensating for the driving transistor.

In the display device according to the present disclosure, the first scan transistor may be an oxide transistor and the second scan transistor may be a silicon transistor.

In the display device according to the present disclosure, the driving transistor may be an oxide transistor or a silicon transistor.

In the display device according to the present disclosure, the driving transistor may have a channel formed of a semiconductor oxide.

In the display device according to the present disclosure, the second scan transistor may be a p-type or n-type metal-oxide-semiconductor silicon transistor or an n-type metal-oxide-semiconductor silicon transistor.

1 2 According to the gate driving circuit and the display device using the same of the present disclosure, it is possible to reduce the size of a bezel by integrating SCand SCdrivers and to secure a sufficient initialization time using 6-phase clock signals.

The foregoing general description and the following detailed description of the present disclosure do not specify essential features of the claims and thus the scope of the claims is not limited by the description.

For embodiments of the present disclosure disclosed in the description, specific structural and functional descriptions are exemplified for the purpose of describing embodiments of the present disclosure, and embodiments of the present invention can be implemented in various forms and are not to be considered as a limitation of the invention.

The present disclosure can be modified in various manners and have various forms and specific embodiments will be described in detail with reference to the drawings. However, the disclosure should not be construed as limited to the embodiments set forth herein, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the embodiments.

While terms, such as “first”, “second”, etc., may be used to describe various components, such components must not be limited by the above terms. The above terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component and the second component may be referred to as the first component without departing from the scope of the present invention.

When an element is “coupled” or “connected” to another element, it should be understood that a third element may be present between the two elements although the element may be directly coupled or connected to the other element. When an element is “directly coupled” or “directly connected” to another element, it should be understood that no element is present between the two elements. Other representations for describing a relationship between elements, that is, “between”, “immediately between”, “in proximity to”, “in direct proximity to” and the like should be interpreted in the same manner.

The terms used in the specification of the present invention are merely used in order to describe particular embodiments, and are not intended to limit the scope of the present invention. An element described in the singular form is intended to include a plurality of elements unless the context clearly indicates otherwise.

In the specification of the present invention, it will be further understood that the terms “comprise” and “include” specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments pertain. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Meanwhile, when a certain embodiment can be implemented in a different manner, a function or an operation specified in a specific block may be performed in a different sequence from that specified in a flowchart. For example, two consecutive blocks may be simultaneously executed or reversely executed according to related function or operation.

Hereinafter, a gate driving circuit and a display device using the same according to the present disclosure will be described with reference to the attached drawings.

In the following description, a pixel circuit and a gate driving circuit formed on a substrate of a display panel may be implemented by n-type or p-type transistors. For example, a transistor may be implemented by a MOSFET (metal oxide semiconductor field effect transistor). The transistor is a three-electrode element including a gate, a source and a drain. The source is an electrode that provides carriers to the transistor. Carriers flow from the source in the transistor. The drain is an electrode through which carriers are emitted in the transistor. For example, carriers flow from the source to the drain in the transistor. In the case of the n-type transistor, carriers are electrons and thus a source voltage is lower than a drain voltage such that the electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type transistor, current flows from the drain to the source. In the case of the p-type transistor, carriers are holes and thus a source voltage is higher than a drain voltage such that the holes can flow from the source to the drain. Since holes flow from the source to the drain in the p-type transistor, current flows from the source to the drain. The source and the drain of a transistor are not fixed and may be interchanged according to voltages applied thereto.

A turn-on voltage of the p-type transistor may be a low-level voltage VL and a turn-off voltage thereof may be a high-level voltage VH. A turn-on voltage of the n-type transistor may be a high-level voltage and a turn-off voltage thereof may be a low-level voltage.

1 FIG. 1 FIG. is a block diagram showing a display device according to an embodiment of the present disclosure. Here,is a block diagram showing an exemplary display device in which pixel circuits that can be externally compensated are arranged and components of the display device are not limited thereto.

10 10 20 30 The display deviceincludes a display panel, a drive integrated circuit (IC), a memory, and the like.

10 A screen displaying an input image in the display panelincludes a plurality of pixels P connected to signal lines. Although the pixels P may include red, green and blue sub-pixels for color representation, the present disclosure is not limited thereto and the pixels P may further include white sub-pixels. An area in which the pixels P are arranged to display images is referred to as a display area (DA) and an area other than the display area DA is referred to as a non-display area, and the non-display area may be called a bezel.

1 2 Signal lines may include data lines through which an analog data voltage Vdata is provided to the pixels P and gate lines through which a gate signal is provided to the pixels P. The gate signal may include two or more signals according to pixel circuit configuration. In a pixel circuit which will be described below, the gate signal includes a first scan signal SC, a second scan signal SCand an emission signal EM. The signal lines may further include sensing lines used to sense electrical characteristics of the pixels P.

10 20 20 20 28 21 28 15 28 20 28 28 25 26 27 The pixels P of the display panelare arranged in a matrix form to constitute a pixel array, but the present invention is not limited thereto. The pixels P can be arranged in various forms such as a pixel sharing form, a stripe form, and a diamond form in addition to the matrix form. Each pixel P can be connected to any one of the data lines, any one of the sensing lines, and at least one of the gate lines. Each pixel P is provided with a high-level power supply voltage and a low-level power supply voltage from a power generator. The power generator can provide the high-level power supply voltage to the pixels P through a high-level power supply voltage line. In addition, the power generator can provide the low-level power supply voltage to the pixels P through a low-level power supply voltage line. The power generator may be included in the drive IC. The drive ICmodules input image data into a predetermined compensation value of a pixel P on the basis of an electrical characteristic sensing result of the pixel P. The drive ICincludes a data driving circuitwhich generates a data voltage corresponding to modulated data V-DATA and a timing controllerwhich controls operation timings of the data driving circuitand a gate driving circuit. The data driving circuitof the drive ICgenerates compensated data by adding a predetermined compensation value to input image data. The data driving circuitconverts the compensated data into a data voltage Vdata and supplies the data voltage Vdata to the data lines. The data driving circuitincludes a data driver, a compensator, a compensation memory, and the like.

25 22 23 The data drivermay include a sensorand a data voltage generator, but the present disclosure is not limited thereto.

21 40 21 15 25 The timing controllercan generate timing signals from video signals input from a host system. For example, the timing controllercan generate a gate timing control signal GTC for controlling an operation timing of the gate driving circuitand a data timing control signal DTC for controlling an operation timing of the data driveron the basis of a vertical synchronization signal, a horizontal synchronization signal, a dot clock signal, and a data enable signal.

23 23 The data timing control signal DTC may include a source start pulse signal, a source sampling clock signal, and a source output enable signal, but the present invention is not limited thereto. The source start pulse signal controls a data sampling start timing of the data voltage generator. The source sampling clock signal is a clock signal that controls a data sampling timing on the basis of rising or falling edges. The source output enable signal controls an output timing of the data voltage generator.

The gate timing control signal GTC may include a gate start pulse signal and a gate shift clock signal, but the present disclosure is not limited thereto. The gate start pulse signal is applied to a stage that generates the first output to activate the operation of the stage. The gate shift clock signal is a clock signal commonly input to stages and shifts the gate start pulse signal.

23 The data voltage generatorgenerates a data voltage Vdata of an input image using a digital-analog converter (DAC) that converts a digital signal into an analog signal in a normal driving mode in which an input image is reproduced on a screen and supplies the data voltage Vdata to the pixels P through the data lines.

23 23 10 30 30 27 30 In a sensing mode for measuring electrical characteristic deviations of pixels P before product shipping or during operation of products, the data voltage generatorconverts test data received from a grayscale-luminance measurement system to generate a data voltage for sensing. The data voltage generatorsupplies the data voltage for sensing to a sensing target pixel P of the display panelthrough data lines. The grayscale-luminance measurement system senses electrical characteristics of the pixels P. The grayscale-luminance measurement system derives compensation values of the pixels P which compensate for electrical characteristic deviations of the pixels P, particularly, threshold voltage deviations of driving transistors on the basis of a sensing result. The grayscale-luminance measurement system stores the compensation values of the pixels P in the memoryor updates pre-stored values. The memorymay be implemented as the compensation memoryand a single memory. Further, the memorymay be a flash memory, but the present invention is not limited thereto.

30 The grayscale-luminance measurement system can be electrically connected to the memoryin a sensing mode operation.

10 30 27 20 27 20 When power is applied to the display devicein the normal driving mode, a compensation value from the memoryis loaded into the compensation memoryof the drive IC. The compensation memoryof the drive ICmay be a DDR SDRAM or an SRAM, but the present invention is not limited thereto.

22 22 The sensorcan sample a source voltage of a driving transistor according to current of the driving transistor to sense electrical characteristics of the driving transistor. The sensormay be configured to sense electrical characteristics of each pixel P and transmit the electrical characteristics to the grayscale-luminance measurement system in an aging process before product shipping.

26 27 23 The compensatormodulates input image data using the compensation value read from the compensation memoryand transmits the modulated data V-DATA to the data voltage generator.

2 FIG.A 2 FIG.A 2 FIG.A 1 2 3 1 2 3 1 2 3 1 is a circuit diagram showing a pixel circuit of the display device according to an embodiment of the present invention. The pixel circuit ofmay include an emission element EL, a driving transistor DT, a capacitor C, a first scan transistor ST, a second scan transistor ST, and an emission switching transistor ST. The first scan transistor ST, the second scan transistor ST, the emission switching transistor STand the driving transistor DT of the pixel circuit are implemented as two types of transistors. For example, transistor types may include an n type and a p type, and an oxide semiconductor transistor and a polysilicon transistor. The first scan transistor STmay be implemented as an n-type transistor, and the driving transistor, the second scan transistor STand the emission switching transistor STmay be implemented as p-type transistors. Although a pixel circuit in which only the first scan transistor STis implemented as an n-type transistor is exemplified in, the present disclosure is not limited thereto.

1 2 The first scan transistor STof the pixel circuit according to an embodiment of the present disclosure may be an oxide transistor and the second transistor STmay be a silicon transistor. Alternatively, the second scan transistor may be a p-type metal-oxide-semiconductor silicon transistor or an n-type metal-oxide-semiconductor silicon transistor.

In addition, the driving transistor DT may be configured as an oxide transistor or a silicon transistor. The driving transistor DT may include a channel formed of a semiconductor oxide.

2 FIG.A Although an externally and internally compensated pixel circuit composed of four transistors and one capacitor is exemplified in, the present disclosure is not limited thereto and the pixel circuit may be an internally compensated or externally compensated pixel circuit composed of two types of n-type and p-type transistors.

2 FIG.A In, the threshold voltage of the driving transistor DT can be compensated through an external compensation method and mobility deviation of the driving transistor can be compensated through an internal compensation method.

1 As described above, the first scan transistor STmay be an oxide transistor including an oxide semiconductor layer having a small off current. Off current is a leakage current flowing between the source and the drain of a transistor in a state in which the transistor is turned off. A transistor element having a small off current has a small leakage current even if it is in an off state for a long time, and thus luminance variations in pixels can be reduced when the pixels are driven at a low speed. For example, low-speed driving may be driving at 1 Hz.

2 3 The driving transistor DT, the second scan transistor STand the emission switching transistor STmay be polysilicon transistors including a semiconductor layer formed of low temperature polysilicon (LTPS) with high mobility.

In the display device of the present disclosure, a frame rate can be reduced, and pixels are driven at a low speed in order to reduced power consumption in still images. In this case, a data update period increases and thus flicker may occur when a leakage current is generated in pixels. A user can perceive flicker when the luminance of pixels periodically changes.

1 If the first scan transistor STwith a long off period is used as a transistor including an oxide semiconductor layer with a small off current, the leakage current decreases in low-speed driving and thus flicker can be prevented.

2 FIG.A 1 2 1 2 Referring to, a first scan signal SC, a second scan signal SC, and an emission signal EM are applied to the pixel circuit. The first scan signal SC, the second scan signal SCand the emission signal EM swing between the high-level voltage VH and the low-level voltage VL.

The emission element EL includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL), but the present disclosure is not limited thereto. The cathode of the emission element EL is provided with a low-level power supply voltage VSS and the anode is connected to a drain electrode of the driving transistor.

1 The driving transistor DT is a driving element that controls current flowing through the emission element EL according to a gate-source voltage. The driving transistor DT includes a gate electrode connected to a first node DTG, a drain electrode connected to a second node DTD, and a source electrode connected to a third node DTS. The first node DTG is connected to the gate electrode of the driving transistor DT, one electrode of the capacitor C, and the source element of the first scan transistor ST. The capacitor C is connected between the first node DTG and the third node DTS. A high-level power supply voltage VDD is applied to the driving transistor DT through the third node DTS.

1 1 The first scan transistor STincludes a gate electrode to which the first scan signal SCis applied, a drain electrode to which a data voltage Vdata is applied, and a source electrode connected to the gate electrode of the driving transistor DT through the first node DTG.

2 2 2 2 The second scan transistor STis turned on according to the second scan signal SCto form a current path between a sensing line and the second node DTD. The second scan transistor STincludes a gate electrode to which the second scan signal SCis applied, a source electrode to which a reference voltage Vref is applied, and a drain electrode connected to the drain electrode of the driving transistor DT and the anode of the emission element EL through the second node DTD. The reference voltage Vref is lower than the high-level power supply voltage VDD and the data voltage Vdata.

3 The emission switching transistor STincludes a gate electrode to which the emission signal EM is applied, a drain electrode connected to the source electrode of the driving transistor DT through the third node DTS, and a source electrode to which the high-level power supply voltage VDD is applied through the high-level power supply voltage line.

3 The emission switching transistor STis connected between the high-level power supply voltage line through which the high-level power supply voltage VDD is supplied and the source electrode of the driving transistor DT and switches a current path between the high-level power supply voltage line and the driving transistor DT in response to the emission signal EM.

2 FIG.B 2 FIG.A 2 FIG.B 2 FIG.B is a diagram showing scan signal waveforms supplied to the pixel circuit shown in. In(A) and(B), 1H represents 1 horizontal period in which data is written to a pixel.

2 FIG.B 1 2 (A) shows a case in which a logic signal is generated using 6-phase clock signals. The first scan signal SCis a transistor turn-on voltage for 5 horizontal periods 5H and the second scan signal SCis a transistor turn-on voltage for 1 horizontal period 1H.

2 FIG.B 1 2 2 1 1 (B) shows a case in which a logic signal is generated using 8-phase clock signals. The first scan signal SCis a transistor turn-on voltage for 7 horizontal periods 7H and the second scan signal SCis a transistor turn-on voltage for 1 horizontal period 1H. The second scan signal SCis the same logic voltage signal as the first scan signal SCfor an initialization time {circle around (1)} and a logic voltage inverted from the first scan signal SCfor a sampling time {circle around (2)}.

1 1 1 2 2 1 The first scan signal SCis applied to the gate electrode of the first scan transistor STas the high-level voltage VH for 4 horizontal periods 4H or 6 horizontal periods 6H corresponding to the initialization time {circle around (1)}. Accordingly, the first scan transistor STis turned on. The second scan signal SCis also the high-level voltage VH and the second scan transistor STis turned off for the 4 horizontal periods 4H or the 6 horizontal periods 6H. The data voltage Vdata supplied through the drain electrode of the first scan transistor STpasses through the first node DTG connected to the gate electrode of the driving transistor DT and is charged in the capacitor C disposed between the first node DTG and the third node DTS.

2 2 2 2 After lapse of the initialization time {circle around (1)}, the second scan transistor SCswitches to the low-level voltage VL and is applied to the gate electrode of the second scan transistor STso that the second scan transistor STis turned on in the sampling time {circle around (2)} for 1 horizontal period 1H. The reference voltage Vref supplied through the drain electrode of the second scan transistor STis applied to the second node DTD connected to the source electrode of the driving transistor DT.

3 FIG. is a diagram showing a configuration of a scan signal generator in the configuration of the gate driving circuit according to the present disclosure. The gate driving circuit may include an emission signal generator that generates the emission signal EM in addition to the scan signal generator.

15 15 15 15 1 15 15 2 As shown, the gate driving circuitaccording to the present disclosure includes a logic signal generatora, a first scan signal generatorb that shares a node Q and a node QB of the logic signal generatora and generates the first scan signal SC, and a second scan signal generatorc that shares the node Q and the node QB of the logic signal generatora and generates the second scan signal SC.

15 2 2 1 The logic signal generatora receives a start pulse signal VST, a second high-level voltage VGH, a second low-level voltage VGL, and a first clock signal CLKand outputs a carry signal Logic.

15 15 1 1 1 The first scan signal generatorb shares the node Q and the node QB of the logic signal generatora, receives a first high-level voltage VGHand a first low-level voltage VGLand outputs the first scan signal SC.

15 15 2 4 2 The second scan signal generatorc shares the node Q and the node QB of the logic signal generatora, receives the second high-level voltage VGHand a fourth clock signal CKand outputs the second scan signal SC.

4 FIG. 3 FIG. is a diagram showing the configuration of the scan signal generator ofin detail.

15 1 2 7 13 1 2 1 13 The logic signal generatora includes first and second transistors Tand T, seventh to thirteenth transistors Tto T, and first and second bootstrap capacitors CQ and CQB. The first and second transistors Tand Tfrom among the first to thirteenth transistors Tto Toutput a carry pulse signal Logic for starting operation of a shift register subsequent thereto through a node shared thereby.

1 1 1 The first transistor Tincludes a gate electrode connected to a node Q, a source electrode connected to a first clock supply line, and a drain electrode connected to a carry pulse output node. The first transistor Tis turned on or turned off in response to the electric potential of the node Q Q-node to output a logic voltage of the first clock signal CLKthrough an output node or to block the logic voltage.

2 2 2 2 The second transistor Tincludes a gate electrode connected to a node QB, a source electrode connected to a second-high voltage supply line, and a drain electrode connected to the carry pulse output node. The second transistor Tis turned on or turned off in response to the electric potential of the node QB to output the second high-level voltage VGHsupplied through the second high-level voltage line through an output node or to block the second high-level voltage VGH.

7 8 7 2 2 The seventh transistor Tincludes a gate electrode connected to a start pulse line, a source electrode connected to a second low-level voltage line, and a drain electrode connected to the source electrode of the eighth transistor T. The seventh transistor Tis turned on or turned off in response to the electric potential of the start pulse signal VST supplied through the start pulse line to transfer the second low-level voltage VGLsupplied through the second low-level voltage line through the drain electrode or block the second low-level voltage VGL.

8 7 8 6 2 7 2 The eighth transistor Tincludes a gate electrode connected to a sixth clock supply line, the source electrode connected to the drain electrode of the seventh transistor T, and a drain electrode connected to a node Q′. The eighth transistor Tis turned on or turned off in response to the electric potential of a sixth clock signal CLKsupplied through the sixth clock supply line to transfer the second low-level voltage VGLsupplied through the second low-level voltage line and transferred from the seventh transistor Tto the node Q′ or to block the second low-level voltage VGL.

9 9 2 2 The ninth transistor Tincludes a gate electrode connected to the node QB, a source electrode connected to the second high-level voltage line, and a drain electrode connected to the node Q′. The ninth transistor Tis turned on or turned off in response to the electric potential of the node QB to transfer the second high-level voltage VGHsupplied through the second high-level voltage line or to block the second high-level voltage VGH.

10 10 5 2 2 The tenth transistor Tincludes a gate electrode connected to a fifth clock line, a source electrode connected to the second low-level voltage line, and a drain electrode connected to the node QB QB-node. The tenth transistor Tis turned on or turned off in response to the electric potential of a fifth clock signal CLKsupplied through the fifth clock line to transfer the second low-level voltage VGLsupplied through the second low-level voltage line to the node QB QB-node or to block the second low-level voltage VGL.

11 11 2 2 The eleventh transistor Tincludes a gate electrode connected to the start pulse line, a source electrode connected to the second high-level voltage line, and a drain electrode connected to the node QB. The eleventh transistor Tis turned on or turned off in response to the electric potential of the start pulse signal VST supplied through the start pule line to transfer the second high-level voltage VGHsupplied through the second high-level voltage line to the node QB or to block the second high-level voltage VGH.

12 12 2 2 The twelfth transistor Tincludes a gate electrode connected to the node Q′, a source electrode connected to the second high-level voltage line, and a drain electrode connected to the node QB. The twelfth transistor Tis turned on or turned off in response to the electric potential of the node Q′ to transfer the second high-level voltage VGHsupplied through the second high-level voltage line or to block the second high-level voltage VGH.

13 13 2 The thirteenth transistor Tincludes a gate electrode connected to the second low-level voltage line, a source electrode connected to the node Q′, and a drain electrode connected to the node Q. The thirteenth transistor Tis turned on all the time according to the second low-level voltage VGHsupplied through the second low-level voltage line to transfer the logic voltage of the node Q′ to the node Q.

13 One end of the first bootstrap capacitor CQ is connected to the node Q and the other end is connected to the carry pulse output node. Current supplied through the thirteenth transistor Tis charged in the first bootstrap capacitor CQ.

2 One end of the first bootstrap capacitor CQB is connected to the second high-level voltage line and the other end is connected to the node QB. Current corresponding to a voltage according to a difference between the second high-level voltage VGHsupplied through the second high-level voltage line and the electric potential of the node QB is charged in the second bootstrap capacitor CQB.

15 3 4 14 The first scan signal generatorb may include a third transistor T, a fourth transistor Tand a fourteenth transistor Twhich constitute an output unit.

14 15 3 14 2 15 3 14 3 15 14 14 The fourteenth transistor Tincludes a gate electrode connected to the second low-level voltage line, a source electrode connected to node Q′ of the logic signal generatora, and a drain electrode connected to a gate electrode of the third transistor T. The fourteenth transistor Tis turned on all the time according to the second low-level voltage VGLsupplied through the low-level voltage line to transfer the logic voltage of the node Q′ of the logic signal generatora to the gate electrode of the third transistor T. That is, the fourteenth transistor Tcauses the logic voltage applied to the gate electrode of the third transistor Tto be consistent with the electric potential of the node Q of the logic signal generatora. The fourteenth transistor Tis one of a signal transmission transistor. The fourteenth transistor Tmay be omitted.

3 14 1 3 15 1 1 1 The third transistor Tincludes a gate electrode connected to the drain electrode of the fourteenth transistor T, a source electrode connected to the first high-level voltage line, and a drain electrode connected to an output node for the first scan signal SC. The third transistor Tis turned on or turned off in response to the electric potential of the node Q of the logic signal generatora transferred through the gate electrode to output the first high-level voltage VGHsupplied through the first high-level voltage line through the output node for the first scan signal SCor to block the first high-level voltage VGH.

4 15 1 4 15 1 1 1 The fourth transistor Tincludes a gate electrode connected to the node QB of the logic signal generatora, a source electrode connected to the first low-level voltage line, and a drain electrode connected to the output node for the first scan signal SC. The fourth transistor Tis turned on or turned off in response to the electric potential of the node QB of the logic signal generatora transferred through the gate electrode to output the first low-level voltage VGLsupplied through the first low-level voltage line through the output node for the first scan signal SCor to block the first low-level voltage VGL.

15 5 6 15 2 The second scan signal generatorc may include fifth and sixth transistors Tand T, a fifteenth transistor T, and a third bootstrap capacitor CQ_SCwhich constitute an output unit.

15 15 5 15 15 2 15 5 15 5 15 The fifteenth transistor Tincludes a gate electrode connected to the second low-level voltage line, a source electrode connected to node Q′ of the logic signal generatora, and a drain electrode connected to a gate electrode of the fifth transistor T. The fifteenth transistor Tis one of a signal transmission transistor. The fifteenth transistor Tis turned on all the time according to the second low-level voltage VGLsupplied through the low-level voltage line to transfer the logic voltage of the node Q′ of the logic signal generatora to the gate electrode of the fifth transistor T. That is, the fifteenth transistor Tcauses the logic voltage applied to the gate electrode of the fifth transistor Tto be consistent with the electric potential of the node Q of the logic signal generatora.

5 15 2 5 15 4 2 4 The fifth transistor Tincludes a gate electrode connected to the drain electrode of the fifteenth transistor T, a source electrode is connected to a fourth clock line, and a drain electrode connected to an output node for the second scan signal SC. The fifth transistor Tis turned on or turned off in response to the electric potential of the node Q of the logic signal generatora transferred through the gate electrode to output a logic voltage of a fourth clock signal CLKthrough the output node for the second scan signal SCor to block the fourth clock signal CLK.

6 15 2 6 15 2 2 2 The sixth transistor Tincludes a gate electrode connected to the node QB of the logic signal generatora, a source electrode connected to the second high-level voltage line, and a drain electrode connected to the output node for the second scan signal SC. The sixth transistor Tis turned on or turned off in response to the electric potential of the node QB of the logic signal generatora transferred through the gate electrode to output the second high-level voltage VGHsupplied through the second high-level voltage line through the output node for the second scan signal SCor block the second high-level voltage VGH.

1 2 1 1 2 2 15 2 15 15 2 15 1 15 4 2 FIG. When the first scan transistor STis implemented as an oxide semiconductor transistor and the second scan transistor STis implemented as a polysilicon transistor in the circuit configured as shown in, they use separate low-level voltages VGL because their low-level voltages are different. For example, the first low-level voltage VGLis used as a low-level voltage VGL provided to the first scan transistor STand the second low-level voltage VGLis used as a low-level voltage VGL provided to the second scan transistor ST. That is, in the second scan signal generatorc, the second low-level voltage VLGis used as both the start pulse signal VST and a clock signal CLK because the clock signal CLK is output. When the first scan signal generatorb and the second scan signal generatorc are integrated as in the present disclosure, for example, when the second low-level voltage VGLof −10V is applied to the node QB QB-node of the first scan signal generatorb and the first low-level voltage VGLprovided to the first scan signal generatorb is −6V, a drain-source voltage Vgs of the fourth transistor Tis applied as “4V” and thus delay can be improved.

5 FIG.A 5 FIG.B 15 15 15 6 is a circuit diagram showing output signals of the logic signal generatora, the first scan signal generatorb and the second scan signal generatorc when the start pulse signal VST and the sixth clock signal CLKrepresent a low-level voltage VL for a period “step 1” andis a waveform diagram at this time.

5 FIG.B 6 As shown in, the start pulse signal VST and the sixth clock signal CLKrepresent the low-level voltage VL in step 1.

7 15 2 8 6 2 13 1 1 1 12 2 2 2 The seventh transistor Tof the logic signal generatora is turned on by receiving the start pulse signal VST through the gate electrode and transfers the second low-level voltage VGLsupplied through the second low-level voltage line through the drain electrode. The eighth transistor Tis turned on by receiving the sixth clock signal CLKthrough the gate electrode to transfer the second low-level voltage VGLto the node Q′. In this case, since the thirteenth transistor Tis turned on all the time, the node Q has the low-level voltage and thus the first transistor Tis turned on. The first transistor Tis turned on and thus the carry output Logic has the high-level voltage of the first clock signal CLK. The twelfth transistor Tis turned on by the second low-level voltage VGLapplied to the gate electrode to transfer the second high-level voltage VGHto the node QB. In this case, the node QB has the high-level voltage and thus the second transistor Tmaintains a turn-off state.

14 15 2 15 3 3 3 1 1 15 4 4 The fourteenth transistor Tof the first scan signal generatorb is turned on by the second low-level voltage VGLsupplied to the gate electrode to transfer the low-level voltage of the node Q of the logic signal generatora to the gate electrode of the third transistor T. The third transistor Tis turned on by the low-level voltage of the node Q applied to the gate electrode. The third transistor Ttransfers the first high-level voltage VGHsupplied to the source electrode to the drain electrode to output the high-level voltage VH as the first scan signal SC. In this case, since the high-level voltage of the node QB of the logic signal generatora is provided to the gate electrode of the fourth transistor T, the fourth transistor Tmaintains a turn-off state.

15 15 2 15 5 5 5 2 15 6 6 The fifteenth transistor Tof the second scan signal generatorc is turned on by the second low-level voltage VGLsupplied to the gate electrode to transfer the low-level voltage of the node Q of the logic signal generatora to the gate electrode of the fifth transistor T. The fifth transistor Tis turned on by the low-level voltage of the node Q applied to the gate electrode. The fifth transistor Ttransfers the high-level voltage supplied to the source electrode and transferred through the fourth clock line to the drain electrode to output the high-level voltage as the second scan signal SC. In this case, since the high-level voltage of the node QB of the logic signal generatora is provided to the gate electrode of the sixth transistor T, the sixth transistor Tmaintains a turn-off state.

6 1 Accordingly, the node Q is charged to the low-level voltage upon synchronization of the start pulse signal VST with the sixth clock signal CLKin step 1, and the initialization period {circle around (1)} starts upon output of the high-level voltage as the first scan signal SC.

6 FIG.A 6 FIG.B 15 15 15 1 is a circuit diagram showing output signals of the logic signal generatora, the first scan signal generatorb and the second scan signal generatorc when the first clock signal CLKrepresents the low-level voltage VL for a period “step 2” andis a waveform diagram at this time.

6 FIG.B 6 1 As shown in, the start pulse signal VST and the sixth clock signal CLKare high-level voltages and the first clock signal CLKis the low-level voltage in step 2.

6 7 8 11 13 2 12 2 2 11 12 1 1 1 15 Since the start pulse signal VST and the sixth clock signal CLKswitch to the high-level voltage, the seventh transistor T, the eighth transistor Tand the eleventh transistor Tare turned off. The node Q′ is floated to the low-level voltage. The thirteenth transistor Treceiving the second low-level voltage VGLthrough the gate electrode maintains a turn-on state, and thus the node Q represents the low-level voltage. As the voltage charged in the first bootstrap capacitor CQ is discharged, the voltage of the node Q has a voltage value lower than the low-level voltage. Since the node Q′ represents the low-level voltage in a floating state, the twelfth transistor Tis turned on. The second transistor Tmaintains a turn-off state because the node QB is provided with the second high-level voltage VGHthrough the source electrodes of the eleventh transistor Tand the twelfth transistor T. The first transistor Tis turned on by the low-level voltage applied to the gate electrode. The first transistor Toutputs the low-level voltage of the first clock signal CLKsupplied to the source electrode to the output terminal through the drain electrode. The output signal Logic of the logic signal generatora switches to the low-level voltage.

3 15 3 1 1 4 15 4 The third transistor Tof the first scan signal generatorb is turned on by the low-level voltage of the node Q applied to the gate electrode. The third transistor Toutputs the first high-level voltage VGHsupplied to the source electrode as the first scan signal SC. In this case, since the high-level voltage of the node QB is provided to the gate electrode of the fourth transistor Tof the first scan signal generatorb, the fourth transistor Tmaintains a turn-off state.

15 15 2 5 5 4 2 6 6 The fifteenth transistor Tof the second scan signal generatorc maintains a turn-on state according to the second low-level voltage VGHsupplied to the gate electrode and the node Q represents the low-level voltage. The fifth transistor Tis turned on by the low-level voltage of the node Q supplied to the gate electrode. The fifth transistor Toutputs the fourth clock signal CLKhaving the high-level voltage supplied to the source electrode as the second scan signal SC. In this case, since the high-level voltage of the node QB is supplied to the gate electrode of the sixth transistor T, the sixth transistor Tmaintains a turn-off state.

2 15 4 15 5 1 15 2 15 2 3 4 15 2 The output signal SCof the second scan signal generatorc is synchronized with the fourth clock signal CLK. Accordingly, the output signals of the first scan signal generatorb and the second scan signal generatorc maintain a floating state in periods “step 3” and “step 4”. That is, since the output signal SCof the first scan signal generatorb is the high-level voltage and the output signal SCof the second scan signal generatorc maintains the low-level voltage when the second clock signal CLKand the third clock signal CLKare at the low-level voltage, there is no phase change. In step 5 in which the fourth clock signal CLKis toggled, the second scan signal generatorc outputs the second scan signal SC.

7 FIG.A 7 FIG.B 15 15 15 4 is a circuit diagram showing output logic signals of the logic signal generatora, the first scan signal generatorb and the second scan signal generatorc when the fourth clock signal CLKrepresents the low-level voltage VL for a period “step 5” andis a waveform diagram at this time.

7 FIG.B 4 7 8 11 6 As shown in, the fourth clock signal CLKis the low-level voltage in step 5. Here, the seventh transistor T, the eighth transistor Tand the eleventh transistor Tmaintain a turn-off state because the start pulse signal VST and the sixth clock signal CLKmaintain the high-level voltage. The electric potential of the node Q′ is the low-level voltage and thus the node Q′ maintains a floating state.

13 2 13 The thirteenth transistor Tis turned on because the second low-level voltage VGLis supplied to the gate electrode of the thirteenth transistor Tand thus the electric potential of the node Q is the low-level voltage.

12 2 11 12 2 Since the electric potential of the node Q′ in the floating state is the low-level voltage, the twelfth transistor Tis turned on and thus the node QB switches to the high-level voltage according to the second high-level voltage VGHprovided through the source electrodes of the eleventh transistor Tand the twelfth transistor Tand the second transistor Tmaintains a turn-off state.

1 1 1 15 2 2 Since the first transistor Tis turned on by the low-level voltage applied to the gate electrode, the first clock signal CLKhaving the high-level voltage applied to the source electrode is output through the drain electrode of the first transistor T. Accordingly, the output signal of the logic signal generatora represents the high-level voltage. Here, since the high-level voltage of the node QB is provided to the gate electrode of the second transistor T, the second transistor Tmaintains a turn-off state.

3 15 3 1 4 4 The third transistor Tof the first scan signal generatorb is turned on by the low-level voltage VL of the node Q applied to the gate electrode. The third transistor Tis turned on to output the first high-level voltage VGHsupplied to the source electrode through the drain electrode. Since the high-level voltage of the node QB is provided to the gate electrode of the fourth transistor T, the fourth transistor Tmaintains a turn-off state.

15 15 2 5 5 4 2 6 6 The fifteenth transistor Tof the second scan signal generatorc maintains a turn-on state according to the second low-level voltage VGLsupplied to the gate electrode and thus the node Q represents the low-level voltage. The fifth transistor Tis turned on by the low-level voltage of the node Q applied to the gate electrode. The fifth transistor Toutputs the fourth clock signal CLKat the low-level voltage input through the source electrode through the drain electrode as the second scan signal SC. Since the high-level voltage of the node QB is provided to the gate electrode of the sixth transistor T, the sixth transistor Tmaintains a turn-off state.

8 FIG.A 8 FIG.B 15 15 15 5 is a circuit diagram showing output signals of the logic signal generatora, the first scan signal generatorb and the second scan signal generatorc when the fifth clock signal CLKrepresents the low-level voltage VL for a period “step 6” andis a waveform diagram at this time.

8 FIG.B 7 8 11 6 As shown in, the seventh transistor T, the eighth transistor Tand the eleventh transistor Tmaintain a turn-off state because the start pulse signal VST and the sixth clock signal CLKmaintain the high-level voltage for the period “step 6”.

10 5 10 2 2 The tenth transistor Tis turned on by the fifth clock signal CLKat the low-level voltage supplied to the gate electrode. Since the tenth transistor Tis provided with the second low-level voltage VGLthrough the source electrode and transfers the second low-level voltage VGLto the node QB connected to the drain electrode, the electric potential of the node QB changes to the low-level voltage.

9 9 9 2 2 12 1 The ninth transistor Tis turned on because the electric potential of the node QB connected to the gate electrode of the ninth transistor Tchanges to the low-level voltage. The ninth transistor Treceives the second high-level voltage VGHthrough the source electrode and provides the second high-level voltage VGHto the node Q′ connected to the drain electrode. Since the electric potential of the node Q′ switches to the high-level voltage, the electric potential of the node Q switches to the high-level voltage. Since the electric potential of the node Q′ is the high-level voltage, the twelfth transistor Tis turned off. The electric potential of the node Q also switches to the high-level voltage because the electric potential of the node Q′ is the high-level voltage, and thus the first transistor Tis turned off.

10 2 2 2 15 Since the tenth transistor Tis turned on and thus the electric potential of the node QB switches to the low-level voltage, the second transistor Tis turned on. The second transistor Toutputs the second high-level voltage VGHsupplied through the source electrode through the drain electrode. In this case, the output electric potential of the logic signal generatora is the high-level voltage.

3 15 3 4 4 4 1 1 The third transistor Tof the first scan signal generatorb is turned off because the high-level voltage of the node Q is applied to the gate electrode of the third transistor T. In this case, the fourth transistor Tis turned on because the low-level voltage of the node QB is applied to the gate electrode of the fourth transistor T. The fourth transistor Treceives the first low-level voltage VGLthrough the source electrode and outputs the first scan signal SCat the low-level voltage through the drain electrode.

15 15 2 5 6 6 2 2 The fifteenth transistor Tof the second scan signal generatorc maintains a turn-on state according to the second low-level voltage VGLsupplied to the gate electrode, and the node Q switches to the high-level voltage because the electric potential of the node Q′ is the high-level voltage. The fifth transistor Tis turned off because the high-level voltage is supplied to the gate electrode. In this case, the sixth transistor Tis turned on by receiving the low-level voltage of the node QB through the gate electrode. The sixth transistor Toutputs the second high-level voltage VGHsupplied to the source electrode as the second scan signal SCthrough the drain electrode.

9 FIG. 4 FIG. 15 15 15 15 14 15 2 shows a gate driving circuit according to another embodiment of the present disclosure. A first scan signal generatorb′ and a second scan signal generatorc′ according to another embodiment differ from the first scan signal generatorb and the second scan signal generatorc ofin that the fourteenth transistor Tand the fifteenth transistor Tthat are turned on all the time by receiving the second low-level voltage VGLthrough the gate electrodes thereof are not provided.

14 15 2 9 FIG. Since the fourteenth transistor Tand the fifteenth transistor Tare components for preventing the voltage of the node Q′ connected to the source electrodes from leaking by being turned on all the time by receiving the second low-level voltage VGLthrough the gate electrodes thereof, they may be omitted in the embodiment of.

15 4 FIG. The logic signal generatora has the same configuration and operation as those in the embodiment ofand thus description thereof is omitted.

1 2 FIG.B Although an example of generating a logic signal, that is, a carry signal, using 6-phase clock signals has been described in the present embodiment, an initialization time of 7 horizontal periods 7H of the first scan signal SCmay be secured as shown in(B) in an embodiment in which a carry signal is generated using 8-phase clock signals.

1 6 In a circuit including both an oxide semiconductor transistor and a polysilicon transistor in a pixel driving circuit, initialization operation is performed in a driver provided in a gate-in-panel (GIP) instead of being performed according to a DC voltage. Here, delay is generated during initial charging of the second node DTD between the source electrode of the driving transistor DT and the anode of the organic light emitting diode EL. Accordingly, a long initialization time of about 4H, for example, is required. As described above, the gate driving circuit according to the present disclosure can secure an initialization time of 4 horizontal periods 4H using 6-phase clock signals CLKto CLK. Furthermore, the gate driving circuit according to the present disclosure can reduce a bezel size since the first scan signal generator and the second scan signal generator are integrated into a single scan signal generator.

Although preferred embodiments of the present disclosure have been described above, it will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure.