Multi-chip package and memory system

This applicationis a reissue continuation of U.S. patent application Ser. No. 15/366,617, which is an application for reissue of U.S. Pat. No. 9,355,685, now RE48449, which was based on U.S. patent application Ser. No. 14/590,626, filed on Jan. 6, 2015, whichis a continuation of U.S. patent application Ser. No. 13/773,305, filed Feb. 21, 2013,now U.S. Pat. No. 8,929,117, granted on Jan. 6, 2015,which is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-067031, filed Mar. 23, 2012, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate to a multi-chip package and a memory system.

Lately interest has been directed to the SSD (solid-state drive), which carries a memory chip that has NAND-type memory cells as a memory system adopted in a computer system. Different from the magnetic disk device, the SSD has the advantages of a high speed of operation, being lightweight, etc.

Given a limited pin count and assembly area for the transfer controller that executes the access control of the memory chip, to maximize capacity, SSDs can be configured with a multi-chip package that has multiple laminated memory chips.

Embodiments provide a multi-chip package and a memory system associated therewith that can realize greater flexibility for the memory system.

In general, a detailed description according to embodiments will be explained with reference to the included figures. However, the present disclosure is not limited to these embodiments. Here, as an example of the memory chips, the memory chips that have NAND-type memory cells will be explained. However, the object of application for the present embodiment is not limited to the NAND-type memory chips. In addition, in some embodiments, the multiple memory chips may not necessarily be laminated inside the multi-chip package.

According to an embodiment of the present disclosure, a multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

1 FIG. 100 200 200 100 200 is a diagram illustrating an example of the multi-chip package on the SSD according to a first embodiment of the present disclosure. As shown in the figure, the SSDis connected to the personal computer or other host deviceby a standard ATA (Advanced Technology Attachment, SATA) or other communication interface, and it functions as the external memory device of the host device. However, the communication interface connecting the SSDand the host deviceis not limited to the SATA standard. For example, one may also adopt an SAS (Serial Attached SCSI), a PCIe (PCI Express) or various other types of communication interface standards.

100 1 2 200 1 3 2 4 200 3 2 3 1 4 2 1 2 1 The SSDhas a NAND memory, a transfer controllerthat executes data transfer between the host deviceand the NAND memory, a RAMas a volatile memory for temporarily storing the transfer data from the transfer controller, and a power supply circuit. The data sent from the host deviceare stored in the RAMunder the control of the transfer controller. Then, the data are read from the RAMand are written in the NAND memory. The power supply circuitgenerates the internal power supply to drive the transfer controllerand the NAND memory, and the generated internal power is fed to the transfer controllerand the NAND memory.

1 10 11 11 10 2 10 2 10 2 1 FIG. The NAND memoryis composed of several (4 in this example) multi-chip packageseach having multiple (4 in this example) memory chipsa tod. The multi-chip packagesare connected to the transfer controllerby connecting wires of different channels (Ch. 0 to Ch. 3). Here, the multi-chip packages are controlled independently for each channel. Thus, the four multi-chip packagesare connected to the transfer controllerso that they can carry out operations in parallel at the same time. Also, the connection wiring of each channel contains the I/O signal line, the control signal line, and the R/B signal line. In the following sections, the “signal line” may be abbreviated as “signal”. The control signals include the chip-enable signal (CE), the command-latch enable signal (CLE), the address-latch enable signal (ALE), the write-enable signal (WE), the read-enable signal (RE), the write-protect signal (WP), and the data strobe signal (DQS). In the following section, the connection relationship between the multi-chip packageand the transfer controllerin the assembly example shown inwill be taken as Connection Example 1.

2 21 200 200 3 22 3 23 1 3 24 2 The transfer controlleralso has the following parts: a host interface controller (host I/F controller)that executes control of the communication interface with the host deviceand control of the data transfer between the host deviceand the RAM, a RAM controllerthat executes control of read/write of the data for RAM, a NAND controllerthat executes control of data transfer between the NAND memoryand the RAM, and an MPUthat executes the overall control of the transfer controlleron the basis of the firmware.

24 23 10 11 11 10 On the basis of the read instruction/write instruction/deletion instruction from the MPU, the NAND controllersends the I/O signal and the control signal to the multi-chip packageof the desired channel. The memory chipsa tod contained in the multi-chip packageof the corresponding channel can execute the operation corresponding to the contents of the received signal.

2 FIG. 2 FIG. 2 FIG. 10 100 10 2 11 11 10 10 2 is a diagram illustrating another example of assembling the multi-chip packageon the SSDthat is according to the first embodiment of the present disclosure. According to the assembly example shown in, each multi-chip packageis connected to the transfer controllerso that it is controlled by the wiring of 2 channels. That is, the four memory chipsa tod of each multi-chip packageare classified into 2 groups that are each controlled through a different channel. In the following, the connection relationship between the multi-chip packageand the transfer controllerin the assembly example shown inwill be referred to as Connection Example 2.

10 11 11 10 According to the first embodiment of the present disclosure, the internal wiring of the multi-chip packageand the arrangement of the memory chipsa tod are designed appropriately to ensure that after manufacturing of the multi-chip package, any of the connection relationships in Connection Example 1 and Connection Example 2 may be adopted.

3 FIG. 10 100 11 11 130 130 130 130 130 130 11 11 10 130 130 11 11 130 130 11 130 130 11 11 is a diagram illustrating the internal wiring of the multi-chip packagebefore assembly on the SSD. As shown in the figure, the memory chipsa tod each have two chip address-setting pinsa,b. The chip address-setting pinsa,b each are connected to either the power supply potential Vcc or the ground potential Vdd. The supply and ground potentials are connected to the chip address-setting pinsa,b that are included in the memory chipsa tod appropriately to ensure that a unique combination is made in each multi-chip package. The combination of the potentials set at the chip address-setting pinsa,b works as the chip address of the initial state for identifying the memory chipsa tod with respect to each other. In this embodiment, the state when the power supply potential Vcc is connected is taken as H(1), and the state when the ground potential Vdd is connected is taken as L(0). Thus, the state of the chip address-setting pina indicates the high-order digits CADD0 of the chip address CADD, and the state of the chip address-setting pinb indicates the low-order digits CADD1 of the chip address. For example, in the memory chipa, both of the chip address-setting pinsa,b are connected to the ground potential Vdd, and the chip address of “00” is set as the initial state. Also, in the memory chipsb tod, “01”, “10”, and “11” are set as the chip addresses of their initial states, respectively.

11 11 123 11 11 123 123 130 130 123 2 In one embodiment, the memory chipsa tod each have a chip address register (chip address memory region)for storing the set value of the chip address. The memory chipsa tod can each use the value stored in the chip address registerincluded in their own memory chip as the chip address set for their own memory chip. The chip address registerstores the chip addresses CADD0, CADD1 input from the chip address-setting pinsa,b as the chip addresses of the initial state. Furthermore, the chip address registercan be configured to allow rewrite of the stored chip address of the initial state by the prescribed command (such as test command) from the transfer controller.

140 10 10 11 11 140 11 11 140 140 56 140 140 56 140 11 11 11 11 Also, the I/O signal line, the R/B signal line, and the control signal line (especially CE) are commonly connected as part of the internal wiringin a multi-chip package to separate sub-groups of the memory chips, where each sub-group of memory chips includes fewer memory chips that the total number of the memory chips that form the multi-chip packageinside the same multi-chip package. For example, memory chipa and memory chipb are commonly connected to each other by the various types of signal lines by the internal wiringand form one signal line group, and memory chipc and memory chipd are commonly connected by the various types of the signal lines by the internal wiringand form another signal line group. The internal wiringis connected to the solder balls (terminals)arranged for the various portions of the internal wiring, respectively. In other words, the internal wiringfor each signal line group is connected to a different solder ball (terminal)and the internal wiringfor other signal line groups. In addition, the signal line group that makes common connections for memory chipa and memory chipb is denoted as the 0-series signal line group, and the CE line, R/B line, and I/O line that form the 0-series signal line group are represented by CE0, R/B0, and I/O-0, respectively. Similarly, the signal line group that commonly connects memory chipc and memory chipd is represented by the 1-series signal line group. The CE line, R/B line, and I/O line that form the 1-series signal line group are denoted as CE1, R/B1, and I/O-1, respectively.

10 10 11 11 In this way, the multi-chip packagehas an arrangement in which the various types of signal lines are commonly connected for each group of the memory chips in a number smaller than the number of the memory chips that form the multi-chip packageinside the multi-chip package, and, at the same time, the various memory chipsa tod can be installed in a multi-chip package according to either Connection Example 1 or Connection Example 2 without being specifically manufactured for either connection example.

4 FIG. 10 100 210 10 2 23 10 2 10 2 10 2 11 11 123 11 11 is a diagram illustrating an example of wiring when the multi-chip packageis assembled on the SSDwith the connection relationship according to Connection Example 1. When Connection Example 1 is adopted, the 0-series signal line group and the 1-series signal line group are combined in a single connection wiringout of the multi-chip package, and they are connected as a single-chamber signal line group to the transfer controller(or more accurately, NAND controller). That is, the CE0 and CE1 are connected out of the multi-chip package, and they are connected to the transfer controller. Similarly, R/B0 and R/B1 are connected out of the multi-chip package, and they are connected to the transfer controller, and I/O-0 and I/O- 1 are connected out of the multi-chip package, and they are connected to the transfer controller. The memory chipsa tod do not execute rewrite of the contents of the chip address registersequipped in them. That is, in operation, “00”, “01”, “10” and “11” are adopted as the chip addresses of the initial state of the memory chipsa tod, respectively.

5 FIG. 10 100 2 23 210 123 11 11 11 11 11 11 is a diagram illustrating an example of wiring when the multi-chip packageis assembled on the SSDwith the connection relationship in Connection Example 2. When Connection Example 2 is adopted, the 0-series signal line group and the 1-series signal line group are independently connected to the transfer controller(or more accurately, NAND controller) because the signal line groups with different channels use separate portions of the connection wiring. Then, after start up, the contents of the chip address registersdisposed in the memory chipsc andd are rewritten to the chip addresses that can identify the memory chipsc andd that are connected to the 1-series signal line group. That is, the chip address of “00” is set as the chip address of memory chipc, and the chip address of “01” is set as the chip address of memory chipd.

6 FIG. 7 FIG. 6 FIG. 10 10 is a diagram illustrating the layout of 1 multi-chip package.is a cross-sectional view illustrating the multi-chip packagetaken across II-II as shown in.

51 11 53 11 53 11 53 11 11 51 54 On the substrate, the following parts are sequentially laminated: a memory chipa, a spacer, a memory chipb, a spacer, a memory chipc, a spacer, and a memory chipd. As the bottom layer, the memory chipa is anchored to the substrateby an underfillmade of a resin.

51 52 11 11 52 51 55 11 11 55 51 57 56 51 56 52 1 2 3 100 2 56 52 55 11 11 On the substrate, multiple terminals (bonding pads)are arranged. The pins disposed in the memory chipsa tod are electrically connected to the terminalson the substratevia the bonding wires. The multiple memory chipsa tod and the bonding wireslaminated onto the substrateare sealed off by the molding resin. Also, solder ballsare arranged on the lower surface of the substrate. The solder ballsare electrically connected to the terminals. The NAND memory, for example, is soldered and assembled together with the transfer controllerand the RAMon a printed circuit board equipped in the SSD. The various types of signals from the transfer controllerare input via the solder balls, the terminals, and the bonding wiresto the pins equipped in the memory chipsa tod.

10 In the above, the multi-chip packagehas been explained with a BGA (Ball Grid Array) package structure. However, it may also have a PGA (Pin Grid Array) package structure or other package structure.

8 FIG. 56 10 51 56 56 is a diagram illustrating an example of a configuration of the solder ballsof the multi-chip package. As shown in the figure, on the substrate, solder ballsare provided that constitute the 0-series signal line group (R/E0 terminals) CE0, CLE0, ALE0, WE0, RE0, WP0, DQS0, I/O-0, (I/O 0-0 to I/O 7-0), and solder ballsare provided that constitute the 1-series signal line group (R/E1 terminals) CE1, CLE1, ALE1, WE1, RE1, WP1, DQS1, I/O-1, (I/O 0-1 to I/O 7-1).

56 56 In this figure, the blank solder ballsindicate unused solder balls.

11 11 11 11 11 In the following section, the composition of the memory chipsa tod will be explained in detail. The memory chipsa tod have the same composition so that in the following only the composition of memory chipa will be explained as a typical memory chip.

9 FIG. 11 11 111 112 113 114 115 116 117 118 119 120 121 122 123 is a block diagram illustrating the composition of memory chipa. As shown in the figure, memory chipa has an I/O signal processor, a control signal processor, a chip controller, a command register, an address register, a data register, a memory cell array, a column decoder, a sense amplifier, a row decoder, an RY/BY (ready/busy) generator, a chip address-setting circuit, and the chip address register.

113 112 11 121 113 Here, the chip controlleris a state transition circuit (also known as a so-called “state machine”) that transitions the state (for example, “ready” or “busy”) on the basis of the various types of control signals received via the control signal processor, and it controls the overall operation of the memory chipa. The RY/BY generatormakes transitions between the ready state (R) and the busy state (B) for the state of the RY/BY signal line under the control of the chip controller.

111 2 111 115 114 116 The I/O signal processoris a buffer circuit for transceiving the I/O signal with the transfer controllervia the I/O signal line. The I/O signal processordistributes the address, command, and data (i.e., write data) fetched as the I/O signal to the address register, the command register, and the data registerfor storage, respectively.

11 2 111 115 Because the I/O signal line is an 8-bit signal line, the I/O signal line can transfer 8-digit addresses en bloc. In contrast, at present the memory capacity of each memory chipa is high enough that in many case the digit number of the address sent from the transfer controlleris over 8. Consequently, in the I/O signal processor, the address of the access destination is divided into multiple rounds for transmission via the 8-bit I/O signal line. The address registerstores the address that has been divided for sending in multiple rounds, and it then combines them into a single address.

11 113 120 118 The high-order 2 bits of the combined address are adopted as the chip identification bits for identifying memory chipa. Thus, the combined address contains the following contents counting from the highest order: a chip identification bit (chip address), a row address, and a column address. The chip address is read by the chip controller, the row address is read by the row decoder, and the column address is read by the column decoder.

117 200 The memory cell arrayhas a composition such that the NAND type memory cells are arranged as a matrix, and it stores the write data from the host device.

120 118 119 117 113 120 118 119 118 116 120 118 119 116 116 111 111 2 The row decoder, the column decoder, and the sense amplifierexecute access to the memory cell arrayunder the control of the chip controller. More specifically, the row decoderselects the word line corresponding to the read row address, and it activates the selected word line. The column decoderselects and activates the bit line corresponding to the read column address. The sense amplifierapplies a voltage on the bit line selected by the column decoder, and it writes the data stored in the data registerto the memory cell transistor located at the cross point between the word line selected by the row decoderand the bit line selected by the column decoder. Also, the sense amplifierreads the data stored in the memory cell transistor via the bit line, and it stores the read data in the data register. The data stored in the data registeris sent via the data line to the I/O signal processor, and it is then transferred from the I/O signal processorto the transfer controller.

112 111 112 113 The control signal processorreceives input from various types of control signals, and on the basis of the received control signals, it executes allotment of the I/O signal received by the I/O signal processorto the register of the storage destination. In addition, the control signal processortransfers the received control signal to the chip controller.

122 130 130 123 113 123 114 11 At start up, the chip address-setting circuitsets the 2-bit chip address set values (CADD0, CADD1) that are externally input via the chip address-setting pinsa,b as the chip address of the initial state in the chip address register. The chip controllercompares the chip address stored in the chip address registerwith the chip address input from the command registerand determines whether its own memory chipa makes a request for operation.

111 112 113 114 115 123 2 The I/O signal processor, the control signal processor, the chip controller, the command registerand the address registeroperate as the address rewrite module that rewrites the chip address stored in the chip address registerby the operation under the control of the transfer controller.

10 100 10 100 1 1 2 10 210 140 2 2 123 2 3 2 123 24 11 11 11 11 1 2 10 210 2 56 140 4 3 4 10 10 FIG. In the following, the method for assembling the multi-chip packageon the SSDwill be explained.is a flow chart illustrating the method for assembling the multi-chip packageon the SSDin the first embodiment. Initially, the manufacturer makes a decision as to whether Connection Example 1 or Connection Example 2 will be adopted (step S). When Connection Example 2 is adopted (NO in step S), the manufacturer connects the transfer controllerand the multi-chip packageto each other by the signal line group (connection wiring) for each portion of the internal wiring. In other words, each signal line group is independently coupled to the transfer controller. (step S). Next, the manufacturer sets the transfer controllerby rewriting the contents of the chip address registerwhen the transfer controlleris started up (step S). Here, the operation of the transfer controlleris set so that the content of the chip address registerthat is rewritten at start up refers to operation, and the firmware that controls the MPUis set so that the test command is issued to each of the memory chipsc tod so that the chip address of the memory chipc is rewritten by “00” and the chip address of the memory chipd is rewritten by “01”. When Connection Example 1 is adopted (YES in step S), the manufacturer connects the transfer controllerwith the multi-chip packageby the signal line group (connection wiring) that has one end connected to the transfer controllerand has the other end commonly connected to the solder ballfor each portion of the internal wiring(step S). With the operation in step Sor step S, the assembly of the multi-chip packagecomes to an end.

11 FIG. 100 100 122 130 130 123 11 3 2 123 140 12 2 11 11 123 11 11 11 11 2 11 111 112 113 114 115 123 11 111 112 113 114 115 123 2 11 11 13 200 14 is a flow chart illustrating the operation of the SSDwhen Connection Example 1 is adopted. When the SSDis started up, the chip address-setting circuithas the contents set in the chip address-setting pinsa,b stored in the chip address registeras the chip address of the initial state (step S). Then, on the basis of the firmware set in step S, the transfer controllerrewrites the contents of the chip address registerwith a chip address that can be identified among the memory chips commonly connected to the same portion of the internal wiring(step S). For example, the transfer controllerissues the test command to rewrite the chip address of the memory chipc by “00” and the test command to rewrite the chip address of the memory chipd by “01”. Immediately after start up, in the chip address registerof the memory chipsa tod, the chip address of the initial state that can identify the memory chipsa tod is set, so that the transfer controllercan assign the issuing destination of the test command using the chip address of the initial state. In the memory chipc, as the test command is received, the I/O signal processor, the control signal processor, the chip controller, the command register, and the address registerwork together to rewrite the contents of the chip address registerby “00”. Also, in the memory chipd, as the test command is received, the I/O signal processor, the control signal processor, the chip controller, the command register, and the address registerwork together to rewrite the contents of the chip address registerby “01”. Next, the transfer controlleruses the rewritten chip address and the CE signal to select the memory chip of the access destination among the memory chipsa tod (step S) and executes the data transfer between the selected memory chip and the host device(step S). The operation then ends.

12 FIG. 100 100 122 130 130 123 11 11 21 2 123 11 11 22 200 23 is a flow chart illustrating the operation of the SSDwhen Connection Example 2 is adopted. When the SSDstarts up, the chip address setting circuithas the contents set in the chip address-setting pinsa,b as the chip address of the initial state in the chip address registerfor each of memory chipsa tod (step S). Next, the transfer controlleruses the chip address of the initial state stored in the chip address registerand the CE signal to select the memory chip of the access destination among the memory chipsa tod (step S), and executes the data transfer between the selected memory chip and the host device(step S). The operation then ends.

10 11 11 140 56 140 140 11 11 123 11 11 111 112 113 114 115 123 100 100 2 2 123 140 2 As explained above, according to the first embodiment of the present disclosure, the multi-chip packagehas one or more memory chipsa tod (the first group), portions of an internal wiringfor each chip that are common connections of the CE signal for a group of memory chips (the second group) that includes one or more memory chips, and one solder ballfor each of the portions of the internal wiringfor feeding the external CE signal to the internal wiring. Each of the memory chipsa tod has a chip address registerthat operates as the chip address memory region configured to store the rewritten chip address. In addition, each of the memory chipsa tod includes an I/O signal processor, a control signal processor, a chip controller, a command register, and an address registerthat together operate as the address rewrite module for rewriting the chip address stored in the chip address registerby an external operation. Consequently, the manufacturer of the SSDcan adopt the desired connection relationships among the connections of Connection Example 1 and Connection Example 2. Consequently, the design of the SSDcan be highly flexible. For example, when Connection Example 1 is adopted, the transfer controllercan use the chip address in the initial state and the CE signal to assign the memory chip with the access destination. Additionally, when Connection Example 2 is adopted, the transfer controllercan rewrite the chip address of the initial state stored in the chip address registerto the chip address that can identify the chip addresses (that is, the memory chips in the second group) that are commonly connected by the internal wiring. Furthermore, the transfer controllercan use the rewritten chip address and the CE signal to assign the memory chip of the access destination.

11 11 122 11 11 2 11 11 Each of the memory chipsa tod also has a chip address-setting circuitthat operates as the initial value-setting module configured to set the chip address at the initial state, where the chip addresses allow identification of the memory chipsa tod in the chip address memory region belonging to the same memory chip at start up. With such an arrangement, by using the chip address of the initial state immediately after start up, the transfer controllercan identify the memory chipsa tod.

130 130 122 123 In addition, feeding units for providing the chip address in the initial state are not limited to the chip address-setting pinsa,b. For example, one may also adopt a scheme in which the chip address of the initial state is preset in a ROM fuse or other nonvolatile memory, and the chip address-setting circuitreads the chip address of the initial state from the nonvolatile memory and stores it in the chip address register.

10 100 According to the second embodiment, the chip address of the initial state is preset in a ROM fuse as rewritable nonvolatile memory. The manufacturer can directly rewrite the chip address in the nonvolatile memory when the multi-chip packageis assembled on the SSD.

13 FIG. 11 11 10 11 11 11 is a diagram illustrating the composition of the memory chipsa tod that form the multi-chip packageaccording to the second embodiment. Because the memory chipsa tod have the same composition, only the composition of the memory chipa will be explained as a representative. The same reference numbers used above in the first embodiment are adopted here, and they will not be explained in detail again.

11 111 112 113 114 115 116 117 118 119 120 121 117 124 As shown in the figure, the memory chipa has an I/O signal processor, a control signal processor, a chip controller, a command register, an address register, a data register, a memory cell array, a column decoder, a sense amplifier, a row decoder, and an RY/BY generator. A portion of the memory cell arrayis used as the ROM fusethat stores the chip address.

124 111 112 113 114 115 124 2 In the ROM fuse, the chip address of the initial state is pre-stored. The I/O signal processor, the control signal processor, the chip controller, the command register, and the address registerwork together to work as an address rewrite module that rewrites the chip address stored in the ROM fuseunder control of the transfer controller.

14 FIG. 10 100 31 31 124 140 32 11 11 2 10 210 140 33 31 2 10 210 2 56 140 34 33 34 10 is a flow chart illustrating the method for assembling the multi-chip packageon the SSDin the second embodiment. First, the manufacturer decides whether Connection Example 1 will be adopted or Connection Example 2 will be adopted (step S). When Connection Example 2 is adopted (NO in step S), the manufacturer uses a prescribed device to manipulate the chip address rewrite region so that the contents of the ROM fuseare rewritten such that it is possible to identify the memory chips that are commonly connected to the same portion of the internal wiring(step S). That is, the manufacturer rewrites the chip address of the memory chipc with “00”, and it rewrites the chip address of the memory chipd with “01”. Next, the transfer controllerand the multi-chip packageare connected to each other by each signal line group (connection wiring) for each portion of the internal wiring(step S). When Connection Example 1 is adopted (YES in step S), the manufacturer has the transfer controllerand the multi-chip packageconnected to each other by the signal line group (connection wiring) that has one end connected to the transfer controllerand has the other end commonly connected to the solder ballone for each portion of the internal wiring(step S). By the operation of step Sor step S, assembly of the multi-chip packageis completed.

100 100 In this way, according to the second embodiment, in its arrangement, the chip address of the initial state is stored in the ROM fuse as the rewritable nonvolatile memory, and the contents of the ROM fuse can be rewritten externally. Consequently, the manufacturer of the SSDcan adopt the desired connection relationships of either Connection Example 1 or Connection Example 2. Consequently, it is possible to have high flexibility in the design of the SSD.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.