Display apparatus with a crack detection line

This application claims the priority benefit of the Korean Patent Application No. 10-2017-0163671 filed on Nov. 30, 2017 in the Republic of Korea, which is hereby incorporated by reference for all purposes as if fully set forth herein.This Application is a Reissue of U.S. Pat. No. 10,998,391 issued on May 4, 2021, which claims the priority benefit of the Korean Patent Application No. 10-2017-0163671 filed on Nov. 30, 2017 in the Republic of Korea, all of which are hereby expressly incorporated by reference into the present application.

The present disclosure relates to a display apparatus.

With the advancement of information-oriented society, various requirements for display apparatuses for displaying an image are increasing. Therefore, various display apparatuses such as liquid crystal display (LCD) apparatuses, organic light emitting display apparatuses, quantum dot light emitting display apparatuses, and electroluminescence display apparatuses are being used recently.

As a type of display apparatus, organic light emitting display apparatuses and quantum dot light emitting display apparatuses are self-emitting display apparatuses and are better in viewing angle and contrast ratio than LCD apparatuses. Also, since the organic light emitting display apparatuses do not need a separate backlight, it is possible to lighten and thin the organic light emitting display apparatuses, and the organic light emitting display apparatuses are excellent in power consumption. Furthermore, the organic light emitting display apparatuses are driven with a low direct current (DC) voltage, have a fast response time, and are low in manufacturing cost.

Organic light emitting display apparatuses each include a plurality of pixels each including an organic light emitting device and a bank which divides the pixels for defining the pixels. The bank can act as a pixel defining layer. The organic light emitting device includes an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. When a high-level voltage is applied to the anode electrode and a low-level voltage is applied to the cathode electrode, a hole and an electron respectively move to the organic light emitting layer through the hole transporting layer and the electron transporting layer and are combined with each other in the organic light emitting layer to emit light.

However, light emitting devices are easily deteriorated by external factors such as external moisture and oxygen. In order to prevent the deterioration, organic light emitting display apparatuses each include an encapsulation layer for preventing external moisture or oxygen from penetrating into the light emitting devices.

Quantum dot light emitting display apparatuses each include a light emitting structure. The light emitting structure includes an anode electrode, a cathode electrode facing the anode electrode, and a light emitting device disposed between the anode electrode and the cathode electrode. The light emitting device includes a hole transporting layer, a light emitting layer, and an electron transporting layer. The light emitting layer includes a quantum dot material.

1 FIG. 2 FIG. 1 FIG. 3 FIG. is a diagram illustrating a mother substrate on which a plurality of display panels are provided according to a related art.is a cross-sectional view taken along line I-I′ illustrated inand is a cross-sectional view schematically illustrating a display apparatus.is a cross-sectional view for describing a method of forming an inorganic layer of a display apparatus according to a related art.

1 3 FIGS.to Referring to, a mother substrate MS is a substrate for simultaneously manufacturing a plurality of display panels PNL, for convenience of a process. The display panels PNL are individually separated from one another and each act as a display apparatus. A plurality of mother substrates MS are simultaneously formed, and then, are separated from one another through a cutting process or a scribing process.

30 10 20 30 30 30 30 In the display apparatus, an encapsulation layeris formed on a substrateon which an organic light emitting deviceis provided. In this case, the encapsulation layerincludes a first inorganic layera, an organic layerb, and a second inorganic layerc and prevents oxygen or water from penetrating into a light emitting layer.

30 30 10 40 10 30 30 10 40 10 30 30 40 10 3 FIG. The first inorganic layera and the second inorganic layerc are deposited on the substratethrough a chemical vapor deposition (CVD) process. The CVD process, as illustrated in, disposes a maskon the substrateand supplies a gas, including a chemical element constituting the first inorganic layera or the second inorganic layerc, to the substrate. The supplied gas performs a chemical reaction on a surface, disposed in an area where the maskis not provided, of the substrate. Therefore, the first inorganic layera or the second inorganic layerc is formed on the surface, disposed in the area where the maskis not provided, of the substrate.

40 10 40 10 40 10 30 30 40 10 However, in the CVD process, since the maskis spaced apart from the substrateby a certain interval, the gas penetrates into a space between the maskand the substrateand performs a chemical reaction on a surface, disposed in an area where the maskis provided, of the substrate, and for this reason, the first inorganic layera or the second inorganic layerc can be formed on the surface, disposed in the area where the maskis provided, of the substrate.

30 30 40 10 30 30 As described above, if the first inorganic layera or the second inorganic layerc is formed on the surface (for example, a scribing line SL), disposed in the area where the maskis provided, of the substrate, a crack can occur in the first inorganic layera or the second inorganic layerc when performing a cutting process (i.e., a laser cutting process or a mechanical scribing process) of separating the display panels PNL. The crack can be propagated to the inside along an inorganic layer due to an external impact, and water and oxygen which flow in along the propagated crack cause a black spot and a dark line smear.

30 30 10 40 10 In order to overcome a limitation where a step coverage of the CVD process is low, technology for depositing the first inorganic layera and the second inorganic layerb on the substratethrough an atomic layer deposition (ALD) process is attracting much attention recently. The ALD process is a method which disposes the maskon the substrateand forms a thin layer by alternating a raw material including an ALD metal and a reactant gas. The ALD process is better in adsorbing force than the CVD process, is high in step coverage, and adjusts a thickness of a thin layer. Accordingly, the ALD process is easy to form a very thin layer.

30 30 40 10 30 30 However, since the ALD process has an excellent absorbing force as described above, the first inorganic layera or the second inorganic layerc can be long formed up to the inside of a region, where the maskis disposed, of the substrate, and for this reason, in comparison with the CVD process, the ALD process has a high possibility that the first inorganic layera or the second inorganic layerc is formed up to the scribing line SL.

40 20 10 30 30 40 20 40 In order to solve the above-described problem, it can be considered to develop a method which disposes the maskat a position close to the light emitting deviceto reduce a separation distance to the substrateand prevents the first inorganic layera or the second inorganic layerc from penetrating into a region where the maskis disposed. However, the method has a problem where the organic light emitting deviceis damaged or deformed by disposing the mask, causing a black spot.

10 40 40 Moreover, a plurality of metal lines are disposed on the substrate, and for example, metal lines disposed in a non-display area are covered by a thin passivation layer in the CVD process. When a high voltage is instantaneously applied in the CVD process, the passivation layer for protecting the metal lines is torn by the high voltage, and static electricity occurs between the metal lines disposed in the non-display area and the mask. Due to the static electricity, the metal lines are damaged which causes the display panel not to normally operate, and it is unable to reuse the mask.

Moreover, if a crack occurs in an outer region of the display panel of the display apparatus according to the related art, power applied to the display panel is short-circuited or cut off, and due to this, a screen is abnormally displayed, or a driving power is not normally supplied.

Accordingly, the present disclosure is directed to provide a display apparatus that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An aspect of the present disclosure is directed to provide a display apparatus which detects a crack occurring in an outer region of a display panel to decrease an error rate.

Another aspect of the present disclosure is directed to provide a display apparatus in which an organic layer is provided to overlap a crack detection line provided in an outer region of a display panel, thereby reducing the damage of the crack detection line caused by static electricity which occurs in a process of depositing an encapsulation layer.

Additional advantages and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or can be learned from practice of the disclosure. The objectives and other advantages of the disclosure can be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, there is provided a display apparatus including a substrate including a display area where a plurality of pixels are provided and a non-display area surrounding the display area, an encapsulation layer including an inorganic layer and an organic layer and covering the display area, a dam disposed in the non-display area to surround the display area and to block a flow of the organic layer, a pad disposed in one edge of the non-display area and spaced apart from the dam in the non-display area, an auxiliary buffer layer spaced apart from the dam and disposed in the non-display area to overlap an end of the inorganic layer, a power auxiliary line disposed between the dam and the auxiliary buffer layer and electrically connected to the pad to receive a voltage from the pad, and a crack detection line spaced apart from the power auxiliary line and electrically connected to the pad.

In another aspect of the present disclosure, there is provided a display apparatus including a substrate including a display area where a plurality of pixels are provided and a non-display area adjacent to the display area, a pad disposed in one edge of the non-display area, a dam disposed in the non-display area to surround the display area and disposed between the display area and the pad in the non-display area where the pad is disposed, an auxiliary buffer layer disposed in the non-display area and spaced apart from the dam, a power auxiliary line disposed between the display area and the auxiliary buffer layer and electrically connected to the pad, and a crack detection line provided to overlap a bottom of the auxiliary buffer layer and electrically connected to the pad.

It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by scopes of claims.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

In a case where ‘comprise’, ‘have’, and ‘include’ described in the present specification are used, another part can be added unless ‘only~’ is used. The terms of a singular form can include plural forms unless referred to the contrary.

In construing an element, the element is construed as including an error range although there is no explicit description.

In describing a position relationship, for example, when a position relation between two parts is described as ‘on~’, ‘over~’, ‘under~’, and ‘next~’, one or more other parts can be disposed between the two parts unless ‘just’ or ‘direct’ is used.

In describing a time relationship, for example, when the temporal order is described as ‘after~’, ‘subsequent~’, ‘next~’, and ‘before~’, a case which is not continuous can be included unless ‘just’ or ‘direct’ is used.

It will be understood that, although the terms “first”, “second”, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

An X axis direction, a Y axis direction, and a Z axis direction should not be construed as only a geometric relationship where a relationship therebetween is vertical, and can denote having a broader directionality within a scope where elements of the present disclosure operate functionally.

The term “at least one” should be understood as including any and all combinations of one or more of the associated listed items. For example, the meaning of “at least one of a first item, a second item, and a third item” denotes the combination of all items proposed from two or more of the first item, the second item, and the third item as well as the first item, the second item, or the third item.

Features of various embodiments of the present disclosure can be partially or overall coupled to or combined with each other, and can be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure can be carried out independently from each other, or can be carried out together in co-dependent relationship.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

4 FIG. 5 FIG. 4 FIG. 100 100 is a perspective view illustrating a display apparatusaccording to an embodiment of the present disclosure.is a plan view illustrating a first substrate, a source drive integrated circuit (IC), a flexible film, a circuit board, and a timing controller illustrated in. Hereinafter, an example where the display apparatusaccording to an embodiment of the present disclosure is an organic light emitting display apparatus will be mainly described, but the present disclosure is not limited thereto. For example, the display apparatus according to an embodiment of the present disclosure can be implemented as a liquid crystal display (LCD) apparatus, an electroluminescence display apparatus, a quantum dot lighting emitting diode, and an electrophoresis display apparatus, in addition to an organic light emitting display apparatus. All the components of the display apparatus according to all embodiments of the present disclosure are operatively coupled and configured.

4 5 FIGS.and 100 110 140 150 160 170 Referring to, the display apparatusaccording to an embodiment of the present disclosure can include a display panel, a source drive IC, a flexible film, a circuit board, and a timing controller.

110 111 112 112 111 112 The display panelcan include a first substrateand a second substrate. The second substratecan be an encapsulation substrate. The first substratecan be a plastic film or a glass substrate, but is not limited thereto. The second substratecan be a plastic film, a glass substrate, or an encapsulation film, but is not limited thereto.

111 112 A plurality of gate lines, a plurality of data lines, and a plurality of pixels can be provided on one surface of the first substratefacing the second substrate. The plurality of pixels can be respectively provided in a plurality of areas defined by an intersection structure of the gate lines and the data lines.

6 7 FIGS.and Each of the pixels can include a thin film transistor (TFT) and a light emitting device including a first electrode, a light emitting layer, and a second electrode. When a gate signal is input through a corresponding gate line by using the TFT, each of the pixels can supply a current to the light emitting device with a data voltage of a corresponding data line. Therefore, the light emitting device of each pixel can emit light having certain brightness, based on the current. A structure of each pixel will be described below with reference to.

110 5 FIG. The display panel, as in, can be divided into a display area DA where the pixels are provided to display an image and a non-display area NDA which does not display an image. The gate lines, the data lines, and the pixels can be provided in the display area DA. A gate driver and a plurality of pads can be provided in the non-display area NDA.

170 110 110 The gate driver can supply gate signals to the gate lines according to a gate control signal input from the timing controller. The gate driver can be provided as a gate driver in panel (GIP) type in the non-display area NDA outside one side or both sides of the display area DA of the display panel. Alternatively, the gate driver can be manufactured as a driving chip, mounted on the flexible film, and attached on the non-display area NDA outside the one side or both sides of the display area DA of the display panelin a tape automated bonding (TAB) type.

140 170 140 140 140 150 The source driver ICcan receive digital video data and a source control signal from the timing controller. The source drive ICcan convert the digital video data into analog data voltages according to the source control signal and can supply the analog data voltages to the data lines. When the source drive ICis manufactured as a driving chip, the source drive ICcan be mounted on the flexible filmin a chip on film (COF) type or a chip on plastic (COP) type.

110 140 160 150 150 330 The plurality of pads such as data pads can be provided in the non-display area NDA of the display panel. A plurality of lines for connecting the pads to the source drive ICand a plurality of lines for connecting the pads to lines of the circuit boardcan be provided on the flexible film. The flexible filmcan be attached on the pads by using an anisotropic conductive film, and thus, the pads can be connected to the lines of the circuit board.

160 150 160 170 160 160 The circuit boardcan be attached on the flexible filmwhich is provided in plurality. A plurality of circuits implemented as driving chips can be mounted on the circuit board. For example, the timing controllercan be mounted on the circuit board. The circuit boardcan be a printed circuit board (PCB) or a flexible PCB (FPCB).

170 160 170 140 170 140 The timing controllercan receive digital video data and a timing signal from an external system through a cable of the circuit board. The timing controllercan generate the gate control signal for controlling an operation timing of the gate driver and the source control signal for controlling the source drive ICwhich is provided in plurality, based on the timing signal. The timing controllercan supply the gate control signal to the gate driver and can supply the source control signal to the source drive ICs.

6 FIG. 111 is a plan view illustrating an example of the first substrateaccording to a first embodiment of the present disclosure.

6 FIG. 111 120 130 Referring to, the first substratecan be divided into a display area DA and a non-display area NDA. A pad area PA where a plurality of pads are provided, a dam, and a buffer layercan be provided in the non-display area NDA.

A plurality of pixels P for displaying an image can be provided in the display area DA. Each of the pixels P can include a TFT and a light emitting device including a first electrode, a light emitting layer, and a second electrode. When a gate signal is input through a corresponding gate line by using the TFT, each of the pixels P can supply a current to the light emitting device with a data voltage of a corresponding data line. Therefore, the light emitting device of each pixel P can emit light having certain brightness, based on the current.

7 FIG. Hereinafter, a structure of a pixel P in a display area DA according to embodiments of the present disclosure will be described in detail with reference to.

7 FIG. 6 FIG. is a cross-sectional view taken along line I-I′ ofand is a cross-sectional view illustrating an example of a pixel P in a display area.

7 FIG. 210 220 111 112 Referring to, a plurality of TFTsand a plurality of capacitorscan be provided on one surface of the first substratefacing the second substrate.

111 210 111 A buffer layer can be provided on the first substrate, for protecting the TFTsfrom water penetrating through the first substratevulnerable to penetration of water.

210 211 212 213 214 210 212 211 210 212 211 212 211 7 FIG. The TFTscan each include an active layer, a gate electrode, a source electrode, and a drain electrode. In, the TFTsare exemplarily illustrated as being provided as a top gate type where the gate electrodeis disposed on the active layer, but is not limited thereto. That is, the TFTscan be provided as a bottom gate type where the gate electrodeis disposed under the active layeror a double gate type where the gate electrodeis disposed both on and under the active layer.

211 111 211 211 111 The active layercan be provided on the buffer layer of the first substrate. The active layercan be formed of a silicon-based semiconductor material, an oxide-based semiconductor material, and/or the like. A light blocking layer for blocking external light incident on the active layercan be provided on the first substrate.

230 211 230 A gate insulation layercan be provided on the active layer. The gate insulation layercan be formed of an inorganic layer, and for example, can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. However, the present embodiment is not limited thereto.

212 230 212 The gate electrodecan be provided on the gate insulation layer. The gate electrodecan be formed of a single layer or a multilayer which includes one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

240 212 240 An interlayer insulation layercan be provided on the gate electrode. The interlayer insulation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof. However, the present embodiment is not limited thereto.

213 214 240 213 211 1 220 230 214 211 2 220 230 213 214 The source electrodeand the drain electrodecan be provided on the interlayer insulation layer. The source electrodecan be connected to the active layerthrough a contact hole CHwhich passes through the gate insulation layerand the interlayer insulation layer, and the drain electrodecan be connected to the active layerthrough a contact hole CHwhich passes through the gate insulation layerand the interlayer insulation layer. The source electrodeand the drain electrodecan each be formed of a single layer or a multilayer which includes one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof, but are not limited thereto.

220 221 222 221 230 212 222 240 223 224 The capacitorscan each include a bottom electrodeand a top electrode. The bottom electrodecan be provided on the gate insulation layerand can be formed of the same material as that of the gate electrode. The top electrodecan be provided on the interlayer insulation layerand can be formed of the same material as that of each of the source electrodeand the drain electrode.

250 210 220 250 250 A passivation layercan be provided on the TFTsand the capacitors. The passivation layercan act as an insulation layer. The passivation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof. However, the present embodiment is not limited thereto.

260 210 220 250 260 A planarization layerfor planarizing a step height caused by the TFTsand the capacitorscan be provided on the passivation layer. The planarization layercan be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

280 284 260 280 282 283 281 282 281 282 283 281 A light emitting deviceand a bankcan be provided on the planarization layer. The light emitting devicecan include a first electrode, a light emitting layer, and a second electrode. The first electrodecan be a cathode electrode, and the second electrodecan be an anode electrode. An area where the first electrode, the light emitting layer, and the second electrodeare stacked can be defined as an emissive area EA.

281 260 281 214 210 3 250 260 281 The second electrodecan be provided on the planarization layer. The second electrodecan be connected to the drain electrodeof a corresponding TFTthrough a contact hole CHwhich passes through the passivation layerand the planarization layer. The second electrodecan be formed of a metal material, which is high in reflectivity, such as a stacked structure (Ti/Al/Ti) of Al and Ti, a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, or a stacked structure (ITO/APC/ITO) of an APC alloy and ITO. The APC alloy can be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

284 260 281 284 The bankcan be provided on the planarization layerto cover an edge of the second electrode, for dividing a plurality of emissive areas EA. The bankcan be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

283 281 284 283 281 282 The light emitting layercan be provided on the second electrodeand the bank. The light emitting layercan include a hole transporting layer, at least one light emitting layer, and an electron transporting layer. In this case, when a voltage is applied to the second electrodeand the first electrode, a hole and an electron can move to the light emitting layer through the hole transporting layer and the electron transporting layer and can be combined with each other in the light emitting layer to emit light.

283 283 281 284 112 The light emitting layercan be a white light emitting layer which emits white light. In this case, the light emitting layercan be provided to cover the second electrodeand the bank. In this case, a color filter can be provided on the second substrate.

283 283 281 112 Moreover, the light emitting layercan include a red light emitting layer which emits red light, a green light emitting layer which emits green light, or a blue light emitting layer which emits blue light. In this case, the light emitting layercan be provided in an area corresponding to the second electrode, and the color filter can not be provided on the second substrate.

282 283 282 282 The first electrodecan be provided on the light emitting layer. When an organic light emitting display apparatus is implemented in a top emission structure, the first electrodecan be formed of a transparent conductive material (or TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO) capable of transmitting light, or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag. A capping layer can be provided on the first electrode.

290 280 290 283 282 290 An encapsulation layercan be provided on the light emitting device. The encapsulation layerprevents oxygen or water from penetrating into the light emitting layerand the first electrode. To this end, the encapsulation layercan include at least one inorganic layer and at least one organic layer.

290 291 292 293 291 282 292 291 292 283 282 291 293 292 For example, the encapsulation layercan include a first inorganic layer, an organic layer, and a second inorganic layer. In this case, the first inorganic layercan be provided to cover the first electrode. The organic layercan be provided on the first inorganic layer. The organic layercan be provided to have a sufficient thickness, for preventing particles from penetrating into the light emitting layerand the first electrodevia the first inorganic layer. The second inorganic layercan be provided to cover the organic layer.

290 323 322 321 First to third color filters and a black matrix can be provided on the encapsulation layer. The first color filter which is a red color filtercan be provided in a red light emitting part, the second color filter which is a blue color filtercan be provided in a blue light emitting part, and the third color filter which is a green color filtercan be provided in a green light emitting part.

290 111 112 111 112 The encapsulation layerof the first substratecan be bonded to the color filters of the second substrateby an adhesive layer, and thus, the first substratecan be bonded to the second substrate. The adhesive layer can be a transparent adhesive resin, but is not limited thereto.

6 FIG. 111 150 To provide description with reference to, a pad area PA can be disposed in one edge of the first substrate. The pad area PA can include a plurality of pads, and the plurality of pads can be electrically connected to wirings of the flexible filmby an anisotropic conductive film.

120 292 120 292 292 290 A damcan be disposed to surround the display area DA and can block a flow of the organic layer. Also, the damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring the encapsulation layerof a pixel P does not penetrate into the pad area PA.

130 291 293 290 The buffer layercan be spaced apart from the display area DA in the non-display area NDA and can contact the first inorganic layeror the second inorganic layerconfiguring the encapsulation layerof the pixel P.

8 10 FIGS.to Hereinafter, a dam and a buffer layer according to the first embodiment of the present disclosure will be described in detail with reference to.

8 FIG. 6 FIG. 9 FIG. 6 FIG. 10 FIG. 8 FIG. is a cross-sectional view taken along line II-II′ of, andis a cross-sectional view taken along line III-III′ of.is a cross-sectional view illustrating an example where a mask is disposed on a buffer layer of.

8 10 FIGS.to 8 FIG. 210 220 200 210 220 200 111 230 240 In, for convenience of description, a detailed configuration of each of TFTsand capacitorsare omitted, and a TFT substrateincluding the TFTsand the capacitorsis illustrated. The TFT substratecan include a first substrate, a gate insulation layer, and an interlayer insulation layerillustrated in.

8 FIG. 290 120 130 200 200 111 A display apparatus illustrated incan include an encapsulation layer, a dam, and a buffer layer, which are provided on the TFT substrate. Also, the TFT substrateincluding the first substratecan include a display area DA where a plurality of pixels P are provided and a pad area PA where a plurality of pads are provided.

290 280 280 290 290 291 292 293 291 282 292 291 293 292 The encapsulation layercan be provided to cover the light emitting deviceprovided in the display area DA and can prevent oxygen or water from penetrating into the light emitting device. The encapsulation layercan include at least one inorganic layer and at least one organic layer. For example, the encapsulation layercan include a first inorganic layer, an organic layer, and a second inorganic layer. In this case, the first inorganic layercan be provided to cover a first electrode, the organic layercan be provided on the first inorganic layer, and the second inorganic layercan be provided to cover the organic layer.

291 293 291 293 The first and second inorganic layersandcan each be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto. The first and second inorganic layersandcan be deposited through a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, but are not limited thereto.

292 283 292 283 292 292 The organic layercan be formed of a transparent material, for transmitting light emitted from the light emitting layer. The organic layercan be formed of an organic material (for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin) capable of transmitting 99% or more of the light emitted from the light emitting layer. The organic layercan be formed through a vapor deposition process, a printing process, or a slit coating process, which uses an organic material, but is not limited thereto. In other embodiments, the organic layercan be formed through an ink-jet process.

120 292 290 292 290 292 293 292 292 292 293 120 292 292 The damcan be provided to surround an outer portion of the display area DA and can block a flow of the organic layerconfiguring the encapsulation layer. The organic layerconfiguring the encapsulation layeris good in coverage performance, but is low in barrier performance. Therefore, the organic layercan be encapsulated by the second inorganic layer. Also, if the organic layerflows into a region where the organic layeris to be formed, water or oxygen penetrates into the inside through the organic layerwhich is exposed without being encapsulated by the second inorganic layer. In order to solve such a problem, the damcan block a flow of the organic layer, thereby preventing the organic layerfrom being exposed at the outside of the display apparatus.

120 292 292 290 292 290 292 120 292 290 292 Moreover, the damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring the encapsulation layerdoes not flow into the pad area PA. When the organic layerconfiguring the encapsulation layerpenetrates into the pad area PA, an electrical contact is not normally made in a pad due to the organic layer, and for this reason, a driving error or a lighting test error occurs. In order to solve such a problem, the damcan block a flow of the organic layerconfiguring the encapsulation layer, thereby preventing the organic layerfrom penetrating into the pad area PA.

8 10 FIGS.to 120 120 292 120 In, one damis illustrated, but the present embodiment is not limited thereto. In other embodiments, the damcan include a first dam and a second dam which is disposed in a non-display area and is spaced apart from the first dam. The second dam can block a flow of the organic layerflowing out to an outer portion of the first dam. Also, the damcan be provided as one or more.

120 260 284 260 284 120 Moreover, the damcan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. In this case, the damcan be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

130 291 293 130 120 140 140 200 291 293 140 130 130 10 FIG. The buffer layercan be spaced apart from the display area DA in a non-display area NDA and can contact at least one of the first inorganic layerand the second inorganic layer. Referring to, for example, the buffer layercan be provided between the damand a scribing line SL, in the non-display area NDA and can support a maskso as to maintain a certain distance between the maskand the TFT substratewhen performing a process of depositing the first inorganic layeror the second inorganic layer. To this end, the maskcan be disposed on the buffer layerto contact the buffer layer.

291 293 140 130 291 293 140 140 200 130 291 293 140 130 120 140 130 130 291 293 130 When the first inorganic layeror the second inorganic layeris deposited after the maskis disposed on the buffer layer, the first inorganic layeror the second inorganic layercan be provided in a region other than a region where the maskis disposed. Also, since a space is not formed between the maskand the TFT substrateby the buffer layer, the first inorganic layeror the second inorganic layeris prevented from penetrating into the region where the maskis disposed. Therefore, in the present embodiment, since the buffer layeris disposed between the damand the scribing line SL and the maskis disposed on the buffer layerto contact the buffer layer, the first inorganic layeror the second inorganic layeris prevented from being formed in an outer portion (for example, the scribing line SL) of the buffer layer.

130 120 291 293 291 293 9 FIG. Moreover, the buffer layercan be provided between the damand the pad area PA as illustrated inand can prevent the first inorganic layeror the second inorganic layerfrom being formed in the pad area PA, thereby solving a problem where a driving error or a lighting test error occurs because an electrical contact is not made in a pad part due to the first inorganic layeror the second inorganic layer.

130 291 293 130 291 293 8 FIG. Moreover, as described above, the buffer layercan contact an edge of at least one of the deposited first inorganic layerand second inorganic layer.illustrates an example where the buffer layercontacts an edge of the first inorganic layerand an edge of the second inorganic layer, but the present embodiment is not limited thereto.

130 293 291 293 291 293 291 293 280 291 293 293 291 292 291 In another embodiment, the buffer layercan contact only an edge of the second inorganic layer. For example, the first inorganic layerand the second inorganic layercan be deposited by using different masks. The first inorganic layercan be deposited by using a first mask, and the second inorganic layercan be deposited by using a second mask. Also, the first mask can be formed greater in area than the second mask, in order for the first inorganic layerto be formed smaller than the second inorganic layerand can be disposed close to the light emitting device. Therefore, the first inorganic layercan be formed less in area than the second inorganic layer. The second inorganic layercan fully cover the first inorganic layerand the organic layerprovided on the first inorganic layer.

130 291 291 293 280 291 140 130 130 291 130 291 293 292 140 130 130 293 293 291 292 In another embodiment, the buffer layercan contact only an edge of the first inorganic layer. For example, the first inorganic layerand the second inorganic layercan be deposited by using different deposition processes. Since the light emitting deviceis not flatly formed, the first inorganic layercan be deposited by using an ALD process which is high in step coverage. The maskcan be disposed on the buffer layerto contact the buffer layer, and then, the first inorganic layercan be deposited by using the ALD process. Therefore, the buffer layercan contact the edge of the first inorganic layer. On the other hand, the second inorganic layercan be provided on the organic layerwhich is relatively flat, and thus, can be deposited by using a CVD process. The maskcan be disposed on the buffer layerso as to be spaced apart from the buffer layer, and then, the second inorganic layercan be deposited by using the CVD process. Therefore, the second inorganic layercan fully cover the first inorganic layerand the organic layer.

2 130 1 120 2 130 1 120 120 140 140 130 291 293 292 120 120 292 280 280 A height Hof the buffer layercan be set equal to or greater than a height Hof the dam. When the height Hof the buffer layeris less than the height Hof the dam, the damis damaged by the maskwhile the maskis being disposed on the buffer layerin a process of depositing the first inorganic layeror the second inorganic layer. Also, when the organic layercontacts the damaged dam, oxygen or water penetrating into the damaged damis absorbed by the organic layerand penetrates into the light emitting device, causing deterioration of the light emitting device.

8 FIG. 2 130 1 120 120 140 130 140 120 140 2 130 1 120 Moreover, as illustrated in, the height Hof the buffer layercan be set greater than the height Hof the dam, and thus, the damage of the damis reduced when disposing the maskon the buffer layer. However, the present embodiment is not limited thereto. When control of the maskis precisely performed, a possibility that the damis damaged by the maskis reduced. In this case, a need where the height Hof the buffer layeris set greater than the height Hof the damis reduced.

130 260 284 260 284 130 Moreover, the buffer layercan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. In this case, the buffer layercan be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

11 FIG. 12 FIG. 11 FIG. 4 FIG. 111 is a plan view illustrating a first substrate of a display apparatus according to a second embodiment of the present disclosure, andis a cross-sectional view taken along line II-II′ of. Here and in the below embodiments, the first substrate in each embodiment can be another example of the first substrateof.

11 12 FIGS.and 7 FIG. 210 220 200 210 220 200 111 230 240 In, for convenience of description, a detailed configuration of each of TFTsand capacitorsare omitted, and a TFT substrateincluding the TFTsand the capacitorsis illustrated. The TFT substratecan include a first substrate, a gate insulation layer, and an interlayer insulation layerillustrated in.

11 FIG. 11 12 FIGS.and 6 10 FIGS.to 200 111 120 130 130 120 Referring to, the TFT substrateincluding the first substratecan be divided into a display area DA and a non-display area NDA, and a pad area PA where a plurality of pads are provided, a dam, and a buffer layercan be provided in the non-display area NDA. Also, the buffer layerillustrated incan be disposed between the damand the display area DA. Hereinafter, therefore, the same descriptions as descriptions given above with reference tocan be omitted or will be briefly given.

120 130 292 130 120 130 292 292 The damcan be disposed to surround an outer portion of the buffer layerin the non-display area NDA and can block a flow of an organic layerflowing out to the outer portion of the buffer layer. Also, the damcan be disposed between the buffer layerand the pad area PA and can block a flow of the organic layerso that the organic layerdoes not penetrate into the pad area PA.

11 12 FIGS.to 120 120 292 120 In, one damis illustrated, but the present embodiment is not limited thereto. In other embodiments, the damcan include a first dam and a second dam which is disposed in the non-display area and is spaced apart from the first dam. The second dam can block a flow of the organic layerflowing out to an outer portion of the first dam. Also, the damcan be provided as one or more.

130 291 293 130 120 140 140 200 291 293 140 130 130 10 FIG. The buffer layercan be provided in the non-display area NDA and can contact at least one of a first inorganic layerand a second inorganic layer. For example, the buffer layercan be provided between the damand the display area DA, in the non-display area NDA and can support a mask(see) so as to maintain a certain distance between the maskand the TFT substratewhen performing a process of depositing the first inorganic layeror the second inorganic layer. To this end, the maskcan be disposed on the buffer layerto contact the buffer layer.

291 293 140 130 291 293 140 140 200 130 291 293 140 130 120 140 130 130 291 293 130 When the first inorganic layeror the second inorganic layeris deposited after the maskis disposed on the buffer layer, the first inorganic layeror the second inorganic layercan be provided in a region other than a region where the maskis disposed. Also, since a space is not formed between the maskand the TFT substrateby the buffer layer, the first inorganic layeror the second inorganic layeris prevented from penetrating into the region where the maskis disposed. Therefore, in the present embodiment, since the buffer layeris disposed between the damand the display area DA and the maskis disposed on the buffer layerto contact the buffer layer, the first inorganic layeror the second inorganic layeris prevented from being formed in an outer portion (for example, a scribing line SL) of the buffer layer.

130 291 293 130 291 293 12 FIG. Moreover, as described above, the buffer layercan contact an edge of at least one of the deposited first inorganic layerand second inorganic layer.illustrates an example where the buffer layercontacts an edge of the first inorganic layerand an edge of the second inorganic layer, but the present embodiment is not limited thereto.

130 291 291 293 280 291 130 130 291 130 291 293 292 200 130 120 293 293 291 293 291 292 291 In another embodiment, the buffer layercan contact only an edge of the first inorganic layer. For example, the first inorganic layerand the second inorganic layercan be deposited by using different deposition processes and different masks. Since a light emitting deviceis not flatly formed, the first inorganic layercan be deposited by using an ALD process which is high in step coverage. A first mask can be disposed on the buffer layerto contact the buffer layer, and then, the first inorganic layercan be deposited by using the ALD process. Therefore, the buffer layercan contact the edge of the first inorganic layer. On the other hand, the second inorganic layercan be provided on the organic layerwhich is relatively flat, and thus, can be deposited by using a CVD process. A second mask can be disposed on the TFT substrateso as to be spaced apart from the buffer layerand the dam, and then, the second inorganic layercan be deposited by using the CVD process. In this case, the second mask can be less in area than the first mask so that the second inorganic layeris formed wider than the first inorganic layer, but can have a large open area. Therefore, the second inorganic layercan fully cover the first inorganic layerand the organic layerprovided on the first inorganic layer.

2 130 1 120 2 130 1 120 120 140 120 140 130 291 293 292 120 120 292 280 280 A height Hof the buffer layercan be set greater than a height Hof the dam. When the height Hof the buffer layeris equal to or less than the height Hof the dam, the damis damaged by the maskcontacting the damwhile the maskis being disposed on the buffer layerin a process of depositing the first inorganic layeror the second inorganic layer. Also, when the organic layercontacts the damaged dam, oxygen or water penetrating into the damaged damis absorbed by the organic layerand penetrates into the light emitting device, causing deterioration of the light emitting device.

2 130 1 120 120 140 130 291 293 Moreover, the height Hof the buffer layercan be set greater than the height Hof the dam, and thus, the damage of the damis reduced when disposing the maskon the buffer layerin a process of depositing the first inorganic layeror the second inorganic layer. However, the present embodiment is not limited thereto.

130 282 130 282 282 140 140 130 291 293 Moreover, the buffer layercan be provided not to overlap a first electrode. In a case where the buffer layeris provided to overlap the first electrode, the first electrodeis damaged because the maskmoves when disposing the maskon the buffer layerin the process of depositing the first inorganic layeror the second inorganic layer. Due to a damaged second electrode, a pixel is not normally driven, and a black spot occurs.

130 282 282 140 130 291 293 According to the present embodiment, the buffer layercan be provided not to overlap the first electrode, and thus, the damage of the first electrodeis reduced when disposing the maskon the buffer layerin the process of depositing the first inorganic layeror the second inorganic layer.

13 FIG. 14 FIG. 13 FIG. is a plan view illustrating a first substrate of a display apparatus according to a third embodiment of the present disclosure, andis a cross-sectional view taken along line II-II′ of.

13 14 FIGS.and 8 FIG. 210 220 200 210 220 200 111 230 240 In, for convenience of description, a detailed configuration of each of TFTsand capacitorsare omitted, and a TFT substrateincluding the TFTsand the capacitorsis illustrated. The TFT substratecan include a first substrate, a gate insulation layer, and an interlayer insulation layerillustrated in.

13 14 FIGS.and 13 14 FIGS.and 6 10 FIGS.to 111 120 132 134 130 132 134 Referring to, the first substratecan be divided into a display area DA and a non-display area NDA, and a pad area PA where a plurality of pads are provided, a dam, a first buffer layer, and a second buffer layercan be provided in the non-display area NDA. Also, a buffer layerillustrated incan include the first buffer layerand the second buffer layer. Hereinafter, therefore, the same descriptions as descriptions given above with reference tocan be omitted or will be briefly given.

120 132 292 132 120 132 292 292 The damcan be disposed to surround an outer portion of the first buffer layerin the non-display area NDA and can block a flow of an organic layerflowing out to the outer portion of the first buffer layer. Also, the damcan be disposed between the first buffer layerand the pad area PA and can block a flow of the organic layerso that the organic layerdoes not penetrate into the pad area PA.

13 14 FIGS.to 120 120 292 120 In, one damis illustrated, but the present embodiment is not limited thereto. In other embodiments, the damcan include a first dam and a second dam which is disposed in the non-display area and is spaced apart from the first dam. The second dam can block a flow of the organic layerflowing out to an outer portion of the first dam. Also, the damcan be provided as one or more.

132 291 132 120 200 291 132 132 The first buffer layercan be provided in the non-display area NDA and can contact an edge of a first inorganic layer. For example, the first buffer layercan be provided between the damand the display area DA, in the non-display area NDA and can support a first mask so as to maintain a certain distance between the first mask and the TFT substratewhen performing a process of depositing the first inorganic layer. To this end, the first mask can be disposed on the first buffer layerto contact the first buffer layer.

291 132 291 200 132 291 132 120 132 132 291 132 When the first inorganic layeris deposited after the first mask is disposed on the first buffer layer, the first inorganic layercan be provided in a region other than a region where the first mask is disposed. Also, since a space is not formed between the first mask and the TFT substrateby the first buffer layer, the first inorganic layeris prevented from penetrating into the region where the first mask is disposed. Therefore, in the present embodiment, since the first buffer layeris disposed between the damand the display area DA and the first mask is disposed on the first buffer layerto contact the first buffer layer, the first inorganic layeris prevented from being formed in an outer portion (for example, a scribing line SL) of the first buffer layer.

132 282 132 282 282 132 291 Moreover, the first buffer layercan be provided not to overlap a first electrode. In a case where the first buffer layeris provided to overlap the first electrode, the first electrodeis damaged because the first mask moves when disposing the first mask on the first buffer layerin the process of depositing the first inorganic layer. Due to a damaged second electrode, a pixel is not normally driven, and a black spot occurs.

132 282 282 132 291 According to the present embodiment, the first buffer layercan be provided not to overlap the first electrode, and thus, the damage of the first electrodeis reduced when disposing the first mask on the first buffer layerin the process of depositing the first inorganic layer.

134 293 134 120 200 293 134 134 The second buffer layercan be provided in the non-display area NDA and can contact an edge of a second inorganic layer. For example, the second buffer layercan be provided between the damand the scribing line SL, in the non-display area NDA and can support a second mask so as to maintain a certain distance between the second mask and the TFT substratewhen performing a process of depositing the second inorganic layer. To this end, the second mask can be disposed on the second buffer layerto contact the second buffer layer.

293 134 293 200 134 293 134 120 134 134 293 134 When the second inorganic layeris deposited after the second mask is disposed on the second buffer layer, the second inorganic layercan be provided in a region other than a region where the second mask is disposed. Also, since a space is not formed between the second mask and the TFT substrateby the second buffer layer, the second inorganic layeris prevented from penetrating into the region where the second mask is disposed. As a result, in the present embodiment, since the second buffer layeris disposed between the damand the scribing line SL and the second mask is disposed on the second buffer layerto contact the second buffer layer, the second inorganic layeris prevented from being formed in an outer portion (for example, the scribing line SL) of the second buffer layer.

132 134 291 293 132 120 134 120 293 292 291 120 291 292 Moreover, according to the present embodiment, since the first buffer layerand the second buffer layerare provided, the first inorganic layerand the second inorganic layercan be provided to have different areas. For example, the first buffer layercan be provided between the damand the display area DA, and the second buffer layercan be provided in an outer portion of the dam, whereby the second inorganic layercan fully cover the organic layer, of which flow is blocked by the first inorganic layerand the dam, to prevent penetration of oxygen and water. In this case, the first inorganic layerand the second inorganic layercan be formed by using the same deposition process or different deposition processes.

2 132 1 120 2 132 1 120 120 132 291 3 134 1 120 3 134 1 120 120 134 293 292 120 120 292 280 280 A height Hof the first buffer layercan be set greater than a height Hof the dam. When the height Hof the first buffer layeris equal to or less than the height Hof the dam, the damis damaged by the first mask while the first mask is being disposed on the first buffer layerin a process of depositing the first inorganic layer. Also, a height Hof the second buffer layercan be set equal to or greater than the height Hof the dam. When the height Hof the second buffer layeris less than the height Hof the dam, the damis damaged by the second mask while the second mask is being disposed on the second buffer layerin a process of depositing the second inorganic layer. Also, when the organic layercontacts the damaged dam, oxygen or water penetrating into the damaged damis absorbed by the organic layerand penetrates into a light emitting device, causing deterioration of the light emitting device.

132 134 260 284 260 284 132 134 The first buffer layerand the second buffer layercan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. In this case, the first buffer layerand the second buffer layercan each be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

15 FIG. 16 FIG. 15 FIG. is a plan view illustrating a first substrate of a display apparatus according to a fourth embodiment of the present disclosure, andis a cross-sectional view taken along line II-II′ of.

15 16 FIGS.and 8 FIG. 210 220 200 210 220 200 111 230 240 In, for convenience of description, a detailed configuration of each of TFTsand capacitorsare omitted, and a TFT substrateincluding the TFTsand the capacitorsis illustrated. The TFT substratecan include a first substrate, a gate insulation layer, and an interlayer insulation layerillustrated in.

15 16 FIGS.and 15 16 FIGS.and 6 10 FIGS.to 111 130 111 Referring to, the first substratecan be divided into a display area DA and a non-display area NDA, and a pad area PA where a plurality of pads are provided and a buffer layercan be provided in the non-display area NDA. Also, the first substrateillustrated indoes not include a dam, and an encapsulation layer does not include an organic layer. Hereinafter, therefore, the same descriptions as descriptions given above with reference tocan be omitted or will be briefly given.

290 280 280 290 290 291 291 282 The encapsulation layercan be provided to cover a light emitting deviceprovided in the display area DA and can prevent oxygen or water from penetrating into the light emitting device. Also, the encapsulation layercan include at least one inorganic layer. For example, the encapsulation layercan include one first inorganic layer. In this case, the first inorganic layercan be provided to cover a first electrode.

291 291 The first inorganic layercan be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto. The first inorganic layercan be deposited through a CVD process or an ALD process, but is not limited thereto.

15 16 FIGS.and 291 291 292 In, one first inorganic layeris illustrated, but the present embodiment is not limited thereto. In other embodiments, an inorganic layer can include a first inorganic layerand a second inorganic layer.

130 291 130 140 140 200 291 140 130 130 The buffer layercan be provided in the non-display area NDA and can contact an edge of the first inorganic layer. For example, the buffer layercan be provided in the non-display area NDA, can be spaced apart from a scribing line SL, and can support a maskso as to maintain a certain distance between the maskand the TFT substratewhen performing a process of depositing the first inorganic layer. To this end, the maskcan be disposed on the buffer layerto contact the buffer layer.

291 140 130 291 140 140 200 130 291 140 130 140 130 130 291 130 When the first inorganic layeris deposited after the maskis disposed on the buffer layer, the first inorganic layercan be provided in a region other than a region where the maskis disposed. Also, since a space is not formed between the maskand the TFT substrateby the buffer layer, the first inorganic layeris prevented from penetrating into the region where the maskis disposed. Therefore, in the present embodiment, since the buffer layeris disposed in the non-display area NDA so as to be spaced apart from the scribing line SL and the maskis disposed on the buffer layerto contact the buffer layer, the first inorganic layeris prevented from being formed in an outer portion (for example, the scribing line SL) of the buffer layer.

130 260 284 260 284 130 Moreover, the buffer layercan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. In this case, the buffer layercan be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

17 FIG. is a plan view illustrating a first substrate of a display apparatus according to a fifth embodiment of the present disclosure.

17 FIG. 18 FIG. 111 120 130 130 130 Referring to, the first substratecan be divided into a display area DA and a non-display area NDA. A pad area PA where a plurality of pads are provided, a dam, and a buffer layercan be provided in the non-display area NDA. Also, the buffer layerillustrated incan be provided in a plurality of island type patterns. The buffer layerprovided in the plurality of island type patterns can be applied to other embodiments.

130 120 130 130 The buffer layercan be provided in the plurality of island type patterns along an outer portion of the dam. According to the fifth embodiment of the present disclosure, since the buffer layeris provided in the plurality of island type patterns instead of a line pattern, an increase in stress caused by forming of the buffer layeris reduced in the non-display area NDA.

18 FIG. is a plan view illustrating a first substrate of a display apparatus according to a sixth embodiment of the present disclosure.

18 FIG. 260 Referring to, a plurality of data lines and a plurality of gate lines intersecting the data lines can be provided in a display area DA. Also, a plurality of pixels P for displaying an image can be provided in a matrix type in a plurality of areas defined by intersections of the data lines and the gate lines in the display area DA. When a gate signal is input through a corresponding gate line, each of the pixels P can supply a current to a light emitting devicewith a data voltage of a corresponding data line. Therefore, the light emitting device of each pixel P can emit light having certain brightness, based on the current. Also, a source voltage can be supplied to a power line. The power line can supply the source voltage to each of the pixels P.

120 130 A dam, a power auxiliary line VAL connected to power lines, a plurality of pads PAD connected to the power auxiliary line VAL, and a buffer layercan be provided in the non-display area NDA. Also, a plurality of data link lines DLL connected to the data lines can be further provided in the non-display area NDA.

111 150 A pad area PA can be disposed in one edge of the first substrate. The pad area PA can include a plurality of pads, and the plurality of pads can be electrically connected to wirings of a flexible filmby an anisotropic conductive film.

120 292 120 292 292 290 The damcan be disposed to surround the display area DA and can block a flow of an organic layer. Also, the damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring an encapsulation layerof a pixel P does not penetrate into the pad area PA.

150 The data link lines DLL can be respectively connected to the pads PAD disposed in the pad area PA and can be respectively connected to the data lines disposed in the display area DA. For example, one end of each of the data link lines DLL can be connected to a corresponding data line through a first contact hole, and the other end can be connected to a corresponding pad PAD through a second contact hole. Each of the plurality of pads PAD can be electrically connected to the wirings of the flexible filmthrough a third contact hole by using an anisotropic conductive film.

Each of the data link lines DLL can be arranged in parallel with a corresponding data line at one end connected to the corresponding data line, and then, can be arranged obliquely with respect to the corresponding data line by a certain length. Also, each of the data link lines DLL can be arranged in parallel with a corresponding pad PAD from an end of the certain length to the other end connected to the corresponding to pad PAD.

212 213 214 The data link lines DLL can be provided in a gate metal pattern including the same material as that of a gate electrode. The data lines and the pads PAD can each be provided in a source/drain metal pattern including the same material as that of a source/drain electrode/.

The power auxiliary line VAL can be arranged in parallel with the gate lines and can be connected to the pad PAD disposed in the pad area PA and the power lines disposed in the display area DA. When the source voltage is applied from the pad PAD, the power auxiliary line VAL can supply the applied source voltage to the power line. In this case, the power auxiliary line VAL can not directly be connected to the power lines but can be connected to the power lines by using connection lines respectively connected to the power lines.

212 213 214 The connection lines can be provided in a gate metal pattern including the same material as that of the gate electrode. The power auxiliary line VAL and the power line can each be provided in a source/drain metal pattern including the same material as that of the source/drain electrode/.

130 291 293 290 291 293 130 The buffer layercan be disposed on a metal pattern (for example, the power auxiliary line VAL to which the source voltage is applied from the pad PAD) in the non-display area NDA and can contact a first inorganic layeror a second inorganic layerconfiguring an encapsulation layerof a pixel P. In the sixth embodiment of the present disclosure, the first inorganic layeror the second inorganic layercan cover a portion of a top of the buffer layer.

19 FIG. Hereinafter, a buffer layer according to the sixth embodiment of the present disclosure will be described in detail with reference to.

19 FIG. 18 FIG. 20 FIG. 19 FIG. 21 FIG. 19 FIG. is a cross-sectional view taken along line III-III′ of, andis a cross-sectional view illustrating an example where a mask is disposed on a buffer layer of.is a cross-sectional view illustrating a modification embodiment of. Hereinafter, a difference with the first embodiment will be mainly described, and the same description as the first embodiment is omitted or may be brief.

19 FIG. 290 120 130 111 111 A display apparatus illustrated incan include an encapsulation layer, a dam, and a buffer layer, which are provided on a first substrate. Also, the first substratecan include a display area DA where a plurality of pixels P are provided and a non-display area NDA, and the non-display area NDA can include a pad area PA where a plurality of pads PAD are provided.

290 280 280 290 290 291 292 293 291 282 292 291 293 292 The encapsulation layercan be provided to cover a light emitting deviceprovided in the display area DA and can prevent oxygen or water from penetrating into the light emitting device. In this case, the encapsulation layercan include at least one inorganic layer and at least one organic layer. For example, the encapsulation layercan include a first inorganic layer, an organic layer, and a second inorganic layer. In this case, the first inorganic layercan be provided to cover a first electrode, the organic layercan be provided on the first inorganic layer, and the second inorganic layercan be provided to cover the organic layer.

120 292 290 292 290 292 293 292 292 292 293 120 292 292 The damcan be provided to surround an outer portion of the display area DA and can block a flow of the organic layerconfiguring the encapsulation layer. The organic layerconfiguring the encapsulation layeris good in coverage performance, but is low in barrier performance. Therefore, the organic layercan be encapsulated by the second inorganic layer. Also, if the organic layerflows into a region where the organic layeris to be formed, water or oxygen penetrates into the inside through the organic layerwhich is exposed without being encapsulated by the second inorganic layer. In order to solve such a problem, the damcan block a flow of the organic layer, thereby preventing the organic layerfrom being exposed at the outside of the display apparatus.

120 292 292 290 292 290 292 120 292 290 292 Moreover, the damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring the encapsulation layerdoes not flow into the pad area PA. When the organic layerconfiguring the encapsulation layerpenetrates into the pad area PA, an electrical contact is not normally made in a pad due to the organic layer, and for this reason, a driving error or a lighting test error occurs. In order to solve such a problem, the damcan block a flow of the organic layerconfiguring the encapsulation layer, thereby preventing the organic layerfrom penetrating into the pad area PA.

19 20 FIGS.and 120 120 292 120 In, one damis illustrated, but the present embodiment is not limited thereto. In other embodiments, the damcan include a first dam and a second dam which is disposed in the non-display area and is spaced apart from the first dam. The second dam can block a flow of the organic layerflowing out to an outer portion of the first dam. Also, the damcan be provided as one or more.

120 260 284 260 284 120 Moreover, the damcan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. In this case, the damcan be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

130 291 293 130 120 140 140 111 291 293 140 130 130 20 FIG. The buffer layercan be provided in a non-display area NDA and can contact an edge of at least one of the first inorganic layerand the second inorganic layer. For example, the buffer layercan be provided between the damand a scribing line SL, in the non-display area NDA and can support a maskso as to maintain a certain distance between the maskand the first substratewhen performing a process of depositing the first inorganic layeror the second inorganic layer. To this end, as illustrated in, the maskcan be disposed on the buffer layerto contact the buffer layer.

291 293 140 130 291 293 140 140 200 130 291 293 140 130 120 140 130 130 291 293 130 When the first inorganic layeror the second inorganic layeris deposited after the maskis disposed on the buffer layer, the first inorganic layeror the second inorganic layercan be provided in a region other than a region where the maskis disposed. Also, since a space is not formed between the maskand a TFT substrateby the buffer layer, the first inorganic layeror the second inorganic layeris prevented from penetrating into the region where the maskis disposed. Therefore, in the present embodiment, since the buffer layeris disposed between the damand the scribing line SL and the maskis disposed on the buffer layerto contact the buffer layer, the first inorganic layeror the second inorganic layeris prevented from being formed in an outer portion (for example, the scribing line SL) of the buffer layer.

130 120 291 293 291 293 Moreover, the buffer layercan be provided between the damand the pad area PA and can prevent the first inorganic layeror the second inorganic layerfrom being formed in the pad area PA, thereby solving a problem where a driving error or a lighting test error occurs because an electrical contact is not made in a pad part due to the first inorganic layeror the second inorganic layer.

291 293 291 293 140 140 140 250 250 250 291 293 In a case where the first inorganic layeror the second inorganic layeris deposited through a CVD process, a high voltage occurs instantaneously in a process of depositing the first inorganic layeror the second inorganic layer. For example, since many electric charges instantaneously concentrate on an edge E of the mask, static electricity occurs between the maskand a power auxiliary line VAL disposed in a region corresponding to the edge E, and for this reason, a defect occurs in both the maskand the power auxiliary line VAL. Although a passivation layeris provided on the power auxiliary line VAL, the passivation layeris very thinly provided, and for this reason, the passivation layercan be torn by the high voltage in the process of depositing the first inorganic layeror the second inorganic layer.

130 140 130 291 293 130 291 293 130 291 293 21 FIG. In order to solve the above-described problem, in the sixth embodiment of the present disclosure, the buffer layercan be provided on a metal pattern (for example, the power auxiliary line VAL) provided in the non-display area NDA. Also, as illustrated in, the maskcan be disposed to cover a portion of a top of the buffer layerin the process of depositing the first inorganic layeror the second inorganic layer. The buffer layercan contact an edge of the first inorganic layeror the second inorganic layer, and a portion of the top of the buffer layercan be covered by the first inorganic layeror the second inorganic layer.

130 140 140 291 293 130 140 Therefore, the buffer layercan be provided between the edge E of the maskand the power auxiliary line VAL, and thus, even when many electric charges instantaneously concentrate on the edge E of the maskin the process of depositing the first inorganic layeror the second inorganic layer, the buffer layerprevents static electricity from occurring between the maskand the power auxiliary line VAL.

130 291 293 130 291 293 20 FIG. A portion of the top of the buffer layer, as described above, can be covered by at least one of the deposited first inorganic layerand second inorganic layer.illustrates an example where a portion of the top of the buffer layeris covered by the first inorganic layerand the second inorganic layer, but the present embodiment is not limited thereto.

293 130 130 293 291 293 280 291 291 140 140 111 291 140 130 130 140 130 In another embodiment, only the second inorganic layercan be provided in only a portion of the top of the buffer layer, and the buffer layercan contact only an edge of the second inorganic layer. In detail, the first inorganic layerand the second inorganic layercan be deposited by using different deposition processes. Since the light emitting deviceis not flatly formed, the first inorganic layercan be deposited by using an ALD process which is high in step coverage. In a case where the first inorganic layeris manufactured through the ALD process, a high voltage does not occur unlike a CVD process, and thus, static electricity does not occur between the maskand the power auxiliary line VAL. Therefore, the maskcan be disposed so as to be spaced apart from the first substrate, and then, the first organic layercan be deposited through the ALD process. In this case, the maskcan be disposed to contact the buffer layer, or can be disposed so as to be spaced apart from the buffer layer. Also, the maskcan be disposed to cover the whole top of the buffer layer.

293 292 140 130 130 293 140 130 293 291 292 The second inorganic layercan be provided on the organic layerwhich is relatively flat, and thus, can be deposited by using a CVD process. The maskcan be disposed on the buffer layerto contact the buffer layer, and then, the second inorganic layercan be deposited by using the CVD process. In this case, the maskcan be disposed to cover a portion of the top of the buffer layer. Therefore, the second inorganic layercan fully cover the first inorganic layerand the organic layer.

22 FIG. 135 250 130 135 Moreover, as illustrated in, at least one groovewhich exposes the passivation layercan be provided in the buffer layer, thereby preventing propagation of a crack. The at least one groovecan be referred to as a crack prevention groove.

130 260 284 260 284 130 Moreover, the buffer layercan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. In this case, the buffer layercan be formed of an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

22 FIG. 22 FIG. 19 FIG. 1 2 is a plan view illustrating a first substrate of a display apparatus according to a seventh embodiment of the present disclosure. In, a power auxiliary line can include a first power auxiliary line VALand a second power auxiliary line VAL. Hereinafter, therefore, description overlapping the description ofis omitted or will be briefly given.

22 FIG. 120 1 2 1 1 130 Referring to, a dam, a first power auxiliary line VALconnected to a plurality of power lines, a second power auxiliary line VALdisposed on the first power auxiliary line VAL, a plurality of pads PAD connected to the first power auxiliary line VAL, and a buffer layercan be provided in a non-display area NDA. Also, a plurality of data link lines DLL connected to a plurality of data lines can be further provided in the non-display area NDA.

A power auxiliary line VAL can be arranged in parallel with a plurality of gate lines and can be connected to the pad PAD disposed in the pad area PA and the power lines disposed in the display area DA. When a source voltage is applied from the pad PAD, the power auxiliary line VAL can supply the applied source voltage to the power line. In this case, the power auxiliary line VAL can not directly be connected to the power lines but can be connected to the power lines by using connection lines respectively connected to the power lines.

1 2 2 1 1 2 1 136 2 1 The power auxiliary line VAL can include the first power auxiliary line VALand the second power auxiliary line VAL. The second power auxiliary line VALcan be provided on the first power auxiliary line VALand can be connected to the first power auxiliary line VALthrough a contact hole. For example, the second power auxiliary line VALcan be connected to the first power auxiliary line VALthrough a contact hole passing through a third buffer layer. In this manner, since the second power auxiliary line VALis additionally provided on the first power auxiliary line VAL, a cross-sectional area of the power auxiliary line VAL increases, and thus, a resistance is reduced, thereby enabling the source voltage to be stably supplied.

212 1 213 214 The connection lines can be provided in a gate metal pattern including the same material as that of a gate electrode. The first power auxiliary line VALand the power line can each be provided in a source/drain metal pattern including the same material as that of a source/drain electrode/.

130 291 293 290 130 136 138 291 293 138 The buffer layercan be disposed on a metal pattern (for example, the power auxiliary line VAL to which the source voltage is applied from the pad PAD) in the non-display area NDA and can contact a first inorganic layeror a second inorganic layerconfiguring an encapsulation layerof a pixel P. In the seventh embodiment of the present disclosure, the buffer layercan include the third buffer layerand a fourth buffer layer, and the first inorganic layeror the second inorganic layercan cover a portion of a top of the fourth buffer layer.

23 24 FIGS.and Hereinafter, the buffer layer according to the seventh embodiment of the present disclosure will be described in detail with reference to.

23 FIG. 22 FIG. 24 FIG. 23 FIG. 23 24 FIGS.and 18 20 FIGS.to 130 136 138 2 136 138 is a cross-sectional view taken along line III-III′ of, andis a cross-sectional view illustrating a modification embodiment of. A buffer layercan be provided on a first substrate illustrated inand can include a third buffer layerand a fourth buffer layer, and a second power auxiliary line VALcan be provided between the third buffer layerand the fourth buffer layer. Hereinafter, therefore, descriptions overlapping the descriptions ofare omitted or will be briefly given.

22 FIG. 290 120 130 111 111 A display apparatus illustrated incan include an encapsulation layer, a dam, and a buffer layer, which are provided on a first substrate. Also, the first substratecan include a display area DA where a plurality of pixels P are provided and a non-display area NDA, and the non-display area NDA can include a pad area PA where a plurality of pads PAD are provided.

130 136 138 136 1 2 136 1 136 150 138 2 The buffer layercan include a third buffer layerand a fourth buffer layer. The third buffer layercan be provided on a first power auxiliary line VALin the non-display area NDA. A second power auxiliary line VALcan be provided on the third buffer layerand can be connected to the first power auxiliary line VALthrough a contact hole which passes through the third buffer layerand a passivation layer. Also, the fourth buffer layercan be provided on the second power auxiliary line VAL.

138 291 293 140 138 291 293 138 291 293 138 291 293 The fourth buffer layercan contact an edge of at least one of a first inorganic layerand a second inorganic layer. A maskcan be disposed to cover only a portion of a top of the fourth buffer layerin a process of depositing the first inorganic layeror the second inorganic layer. Therefore, the fourth buffer layercan contact an edge of the first inorganic layeror the second inorganic layer, and a portion of the top of the fourth buffer layercan be covered by the first inorganic layeror the second inorganic layer.

138 140 2 140 291 293 138 140 2 136 138 140 1 140 291 293 130 138 140 1 The fourth buffer layercan be provided between an edge E of the maskand the second power auxiliary line VAL, and thus, even when many electric charges instantaneously concentrate on the edge E of the maskin the process of depositing the first inorganic layeror the second inorganic layer, the fourth buffer layerprevents static electricity from occurring between the maskand the second power auxiliary line VAL. Also, the third buffer layerand the fourth buffer layercan be provided between the edge E of the maskand the first power auxiliary line VAL, and thus, even when many electric charges instantaneously concentrate on the edge E of the maskin the process of depositing the first inorganic layeror the second inorganic layer, the third buffer layerand the fourth buffer layerprevent static electricity from occurring between the maskand the first power auxiliary line VAL.

138 291 293 138 291 293 23 FIG. A portion of the top of the fourth buffer layer, as described above, can be covered by at least one of the deposited first inorganic layerand second inorganic layer.illustrates an example where a portion of the top of the fourth buffer layeris covered by the first inorganic layerand the second inorganic layer, but the present embodiment is not limited thereto.

293 138 138 293 291 293 280 291 291 140 140 111 291 140 138 138 140 138 In another embodiment, only the second inorganic layercan be provided in only a portion of the top of the fourth buffer layer, and the fourth buffer layercan contact only an edge of the second inorganic layer. For example, the first inorganic layerand the second inorganic layercan be deposited by using different deposition processes. Since a light emitting deviceis not flatly formed, the first inorganic layercan be deposited by using an ALD process which is high in step coverage. In a case where the first inorganic layeris manufactured through the ALD process, a high voltage does not occur unlike a CVD process, and thus, a possibility that static electricity occurs between the maskand the power auxiliary line VAL is reduced. Therefore, the maskcan be disposed so as to be spaced apart from the first substrate, and then, the first organic layercan be deposited through the ALD process. In this case, the maskcan be disposed to contact the fourth buffer layer, or can be disposed so as to be spaced apart from the fourth buffer layer. Also, the maskcan be disposed to cover the whole top of the fourth buffer layer.

293 292 140 138 138 293 140 138 293 291 292 The second inorganic layercan be provided on the organic layerwhich is relatively flat, and thus, can be deposited by using a CVD process. The maskcan be disposed on the fourth buffer layerto contact the fourth buffer layer, and then, the second inorganic layercan be deposited by using the CVD process. In this case, the maskcan be disposed to cover a portion of the top of the fourth buffer layer. Therefore, the second inorganic layercan fully cover the first inorganic layerand the organic layer.

136 138 138 136 23 FIG. 24 FIG. The third buffer layerand the fourth buffer layercan have the same area as illustrated in, but are not limited thereto. In other embodiments, as illustrated in, the fourth buffer layercan have an area which is wider than that of the third buffer layer.

130 260 284 260 284 136 260 260 138 284 284 The buffer layercan be formed at the same time with at least one of a planarization layerand a bankwhich are provided in a pixel P, and can be formed of the same material as that of at least one of the planarization layerand the bank. For example, the third buffer layercan be formed at the same time with the planarization layerand can be formed of the same material as that of the planarization layer. The fourth buffer layercan be formed at the same time with the bankand can be formed of the same material as that of the bank.

18 28 FIGS.to 130 120 130 20 120 130 140 291 293 illustrate an example where the buffer layeris disposed only between the damand the pad area PA, but the present disclosure is not limited thereto. In other embodiments, the buffer layercan be disposed to surround the dam. Also, the buffer layercan be provided in a plurality of island type patterns. Depending on the case, addition to the power auxiliary line VAL, a plurality of metal lines can be disposed in the non-display area NDA. Based on a panel design, the plurality of metal lines can be disposed between the display area DA and the non-display area NDA, or can be disposed in a region, where the pad area PA is not disposed, of the non-display area NDA. Since the buffer layeris provided on the plurality of metal lines, static electricity is prevented from occurring between the edge E of the maskand the metal lines when depositing the first inorganic layeror the second inorganic layerconfiguring the encapsulation layer.

25 FIG. 26 26 FIGS.A toH 25 26 26 FIGS.andA toH 7 10 FIGS.to is a flowchart for describing a method of manufacturing a display apparatus according to a first embodiment of the present disclosure, andare cross-sectional views for describing the method of manufacturing the display apparatus according to the first embodiment of the present disclosure. The manufacturing method will be described below with reference toalong with.

130 52601 First, a pixel P can be formed in a display area DA, and a buffer layercan be formed in a non-display area NDA in operation.

26 FIG.A 250 200 250 250 For example, as in, a passivation layercan be formed on a TFT substrate. The passivation layercan act as an insulation layer. The passivation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof. However, the present embodiment is not limited thereto.

26 FIG.B 260 120 1301 260 120 1301 250 120 1301 120 260 120 1301 250 260 1301 120 1301 120 1301 1301 120 1301 Moreover, as in, a planarization layer, a dam, and a bottom buffer layercan be formed. For example, the planarization layer, the dam, and the bottom buffer layercan be formed on the passivation layer. Also, the damcan be formed in the non-display area NDA, and the bottom buffer layercan be formed outside the dam. The planarization layer, the dam, and the bottom buffer layercan each be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto. The planarization layeris described as being formed of a single layer, but can be formed of two or more layers without being limited thereto. In a case where the planarization layeris formed of two layers such as a top planarization layer and a bottom planarization layer, the buffer layerand the damcan be selectively formed when forming the top planarization layer and the bottom planarization layer. For example, when forming the bottom planarization layer, all of the buffer layerand the damcan be formed, or only the buffer layercan be formed. Also, when forming the top planarization layer, all of the buffer layerand the damcan be formed, or only the buffer layercan be formed.

26 FIG.B 120 1301 260 120 In, the damis illustrated as being formed between the bottom buffer layerand the planarization layer, but is not limited thereto. In other embodiments, the damcan not be formed.

26 FIG.B 1301 120 1301 120 260 Moreover, in, the bottom buffer layeris illustrated as being formed outside the dam, but is not limited thereto. In other embodiments, the bottom buffer layercan be formed between the damand the planarization layer.

26 FIG.B 120 260 120 250 284 In, the damis illustrated as being formed simultaneously with the planarization layer, but is not limited thereto. In other embodiments, the damcan be formed simultaneously with the passivation layeror a bankwhich is to be formed later.

26 FIG.C 3 250 260 224 210 281 281 214 210 281 As in, a contact hole CHwhich passes through the passivation layerand the planarization layerto expose a source or drain electrodeof a TFTcan be formed, and a second electrodecan be formed. The second electrodecan be connected to the drain electrodeof a corresponding TFTthrough. The second electrodecan be formed of a metal material, which is high in reflectivity, such as a stacked structure (Ti/Al/Ti) of Al and Ti, a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, or a stacked structure (ITO/APC/ITO) of an APC alloy and ITO. The APC alloy can be an alloy of Ag, Pd, and Cu.

26 FIG.D 284 1302 284 260 281 284 1302 As in, the bankand the top buffer layercan be formed. For example, the bankcan be formed on the planarization layerto cover an edge of the second electrode, for dividing a plurality of emissive areas EA. The bankand the top buffer layercan each be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but are not limited thereto.

26 FIG.E 283 282 283 281 284 282 283 282 282 As in, a light emitting layerand a first electrodecan be formed. For example, the light emitting layercan be formed on the second electrodeand the bank. Also, the first electrodecan be formed on the light emitting layer. The first electrodecan be formed of a transparent conductive material (or TCO), such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag. A capping layer can be formed on the first electrode.

140 130 2602 140 1302 1302 26 FIG.F Subsequently, a maskcan be disposed on the buffer layerin operation S. For example, as in, the maskcan be disposed on the top buffer layerto contact the top buffer layer.

52603 Subsequently, an inorganic layer can be formed to cover the display area DA in operation.

26 FIG.G 291 292 293 291 291 140 291 As in, a first inorganic layer, an organic layer, and a second inorganic layercan be formed. For example, the first inorganic layercan be formed to cover the display area DA. Also, by using a CVD process or an ALD process, the first inorganic layercan be formed in a region other than a region where the maskis disposed. The first inorganic layercan be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto.

292 291 120 292 283 Subsequently, the organic layercan be formed to cover the first inorganic layerwithout covering the dam. The organic layercan be formed of an organic material (for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin) capable of transmitting 99% or more of light emitted from the light emitting layer, but is not limited thereto.

293 292 293 140 293 Subsequently, the second inorganic layercan be formed to cover the organic layer. In this case, by using a CVD process or an ALD process, the second inorganic layercan be formed in a region other than the region where the maskis disposed. The second inorganic layercan be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto.

26 FIG.G 292 293 291 292 293 292 292 As in, the organic layerand the second inorganic layerare illustrated as being formed on the first inorganic layer, but are not limited thereto. In other embodiments, the organic layerand the second inorganic layercan not be formed. Also, the organic layercan be formed of a double layer. A third inorganic layer can be formed between two layers of the organic layerformed of a double layer.

140 52604 140 140 1302 111 112 26 FIG.H Subsequently, the maskcan be removed in operation. In, a process after the maskis removed is illustrated. For example, the maskdisposed on the top buffer layercan be removed, and then, a first substratecan be bonded to a second substrate. In a case where a plurality of display apparatuses are manufactured by using one mother substrate, a scribing process can be performed for isolating a plurality of display panels formed on the mother substrate into a plurality of display apparatuses. A scribing line SL can be formed between adjacent display panels, and by cutting the display panels along the scribing line SL, each of the display panels can be isolated into one display apparatus.

291 293 130 291 293 280 In the present disclosure, since the first inorganic layerand the second inorganic layerare not formed on the scribing line SL by the buffer layer, a crack is prevented from occurring in the first inorganic layerand the second inorganic layerin the scribing process. Accordingly, the light emitting deviceis prevented from being deteriorated.

27 FIG. 28 28 FIGS.A toL is a flowchart for describing a method of manufacturing a display apparatus according to a second embodiment of the present disclosure, andare cross-sectional views for describing the method of manufacturing the display apparatus according to the second embodiment of the present disclosure.

132 134 52801 First, a pixel P can be formed in a display area DA, and a first buffer layerand a second buffer layercan be formed in a non-display area NDA in operation.

28 FIG.A 250 200 250 250 For example, as in, a passivation layercan be formed on a TFT substrate. The passivation layercan act as an insulation layer. The passivation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof. However, the present embodiment is not limited thereto.

28 FIG.B 260 120 1321 1341 260 120 1321 1341 250 120 1321 1341 1321 120 260 1341 120 Moreover, as in, a planarization layer, a dam, a first bottom buffer layer, and a second bottom buffer layercan be formed. For example, the planarization layer, the dam, the first bottom buffer layer, and the second bottom buffer layercan be formed on the passivation layer. Also, the damcan be formed between the first bottom buffer layerand the second bottom buffer layerin the non-display area NDA. The first bottom buffer layercan be formed between the damand the planarization layerin the non-display area NDA. The second bottom buffer layercan be formed outside the damin the non-display area NDA.

260 120 1321 1341 The planarization layer, the dam, the first bottom buffer layer, and the second bottom buffer layercan each be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

28 FIG.B 120 120 In, the damis illustrated as being formed, but is not limited thereto. In other embodiments, the damcan not be formed.

28 FIG.B 120 260 120 250 284 In, the damis illustrated as being formed simultaneously with the planarization layer, but is not limited thereto. In other embodiments, the damcan be formed simultaneously with the passivation layeror a bankwhich is to be formed later.

28 FIG.C 3 250 260 224 210 281 281 214 210 281 As in, a contact hole CHwhich passes through the passivation layerand the planarization layerto expose a source or drain electrodeof a TFTcan be formed, and a second electrodecan be formed. The second electrodecan be connected to the drain electrodeof a corresponding TFTthrough. The second electrodecan be formed of a metal material, which is high in reflectivity, such as a stacked structure (Ti/Al/Ti) of Al and Ti, a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, or a stacked structure (ITO/APC/ITO) of an APC alloy and ITO. The APC alloy can be an alloy of Ag, Pd, and Cu.

28 FIG.D 284 1322 1342 284 260 281 1322 1322 1342 1342 As in, the bank, a first top buffer layer, and a second top buffer layercan be formed. For example, the bankcan be formed on the planarization layerto cover an edge of the second electrode, for dividing a plurality of emissive areas EA. Also, the first top buffer layercan be formed on the first bottom buffer layer, and the second top buffer layercan be formed on the second bottom buffer layer.

284 1322 1342 The bank, the first top buffer layer, and the second top buffer layercan each be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but are not limited thereto.

28 FIG.E 283 282 283 281 284 282 283 282 282 As in, a light emitting layerand a first electrodecan be formed. For example, the light emitting layercan be formed on the second electrodeand the bank. Subsequently, the first electrodecan be formed on the light emitting layer. The first electrodecan be formed of a transparent conductive material (or TCO), such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag. A capping layer can be formed on the first electrode.

142 132 2802 142 1322 1322 28 FIG.F Subsequently, a first maskcan be disposed on the first buffer layerin operation S. For example, as in, the first maskcan be disposed on the first top buffer layerto contact the first top buffer layer.

291 2803 Subsequently, a first inorganic layercan be formed to cover the display area DA in operation S.

28 FIG.G 291 291 291 140 291 As in, the first inorganic layercan be formed. For example, the first inorganic layercan be formed to cover the display area DA. Also, by using a CVD process or an ALD process, the first inorganic layercan be formed in a region other than a region where the first maskis disposed. The first inorganic layercan be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto.

142 2804 142 132 292 291 120 292 283 28 FIG.H 28 FIG.I Subsequently, the first maskcan be removed in operation S. For example, as in, the first maskdisposed on the first buffer layercan be removed. Also, as in, an organic layercan be formed to cover the first inorganic layerwithout covering the dam. The organic layercan be formed of an organic material (for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin) capable of transmitting 99% or more of light emitted from a light emitting layer, but is not limited thereto.

28 FIG.I 292 291 292 In, the organic layeris illustrated as being formed on the first inorganic layer, but is not limited thereto. In other embodiments, the organic layercan not be formed.

144 134 2805 144 1342 1342 144 142 293 291 28 FIG.J Subsequently, a second maskcan be disposed on the second buffer layerin operation S. For example, as in, the second maskcan be disposed on the second top buffer layerto contact the second top buffer layer. Also, the second maskcan be less in area than the first maskso that the second inorganic layeris formed wider than the first inorganic layer.

293 291 2806 293 292 293 144 293 28 FIG.K Subsequently, a second inorganic layercan be formed on the first inorganic layerin operation S. For example, as in, the second inorganic layercan be formed to cover the organic layer. Also, by using a CVD process or an ALD process, the second inorganic layercan be formed in a region other than the region where the second maskis disposed. The second inorganic layercan be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto.

144 2807 144 134 111 112 28 FIG.L Subsequently, the second maskcan be removed in operation S. For example, as in, the second maskdisposed on the second buffer layercan be removed. Also, a first substratecan be bonded to a second substrate. In a case where a plurality of display apparatuses are manufactured by using one mother substrate, a scribing process can be performed for isolating a plurality of display panels formed on the mother substrate into a plurality of display apparatuses. A scribing line SL can be formed between adjacent display panels, and by cutting the display panels along the scribing line SL, each of the display panels can be isolated into one display apparatus.

29 FIG. 30 FIG. 29 FIG. 31 FIG. 29 FIG. is a plan view illustrating a first substrate of a display apparatus according to an eighth embodiment of the present disclosure.is a cross-sectional view taken along line III-III′ of, andis a cross-sectional view taken along line II-II′ of.

29 31 FIGS.to 111 Referring to, the first substratecan be divided into a display area DA and a non-display area NDA.

210 280 215 280 281 283 282 210 280 280 A plurality of pixels P for displaying an image can be provided in the display area DA. Each of the pixels P can include a TFT, a light emitting device, and an auxiliary electrode. The light emitting devicecan include a second electrode, a light emitting layer, and a first electrode. When a gate signal is input through a corresponding gate line by using the TFT, each of the pixels P can supply a current to the light emitting devicewith a data voltage of a corresponding data line. Therefore, the light emitting deviceof each pixel P can emit light having certain brightness, based on the current.

120 130 180 A pad area PA where a plurality of pads are provided, a dam, a buffer layer, and an auxiliary buffer layercan be provided in the non-display area NDA.

111 A pad area PA can be disposed in one edge of the first substrate. The pad area PA can include the plurality of pads, and the plurality of pads can be electrically connected to wirings of a flexible film by an anisotropic conductive film.

120 122 121 122 121 122 121 292 122 121 292 292 290 The damcan include a first damand a second dam. The first damand the second damcan be disposed to surround the display area DA, and at least one of the first damand the second damcan block a flow of an organic layer. Also, the first damand the second damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring an encapsulation layerof a pixel P does not penetrate into the pad area PA.

130 130 130 291 292 290 The buffer layercan be disposed in the non-display area NDA and can be spaced apart from the display area DA. For example, the buffer layercan be disposed between the display area DA and the pad area PA and can protect lines, connecting the pads PAD in the pad area PA and the pixels P in the display area DA, from static electricity. Also, the buffer layercan support a mask device which is used to form a first inorganic layeror a second inorganic layerconfiguring the encapsulation layer.

180 180 120 120 291 292 290 The auxiliary buffer layercan be disposed in the non-display area NDA and can be spaced apart from the display area DA. For example, the auxiliary buffer layercan be spaced apart from the second damof the damin the non-display area NDA and can support the mask device which is used to form the first inorganic layeror the second inorganic layerconfiguring the encapsulation layer.

120 130 180 30 31 FIGS.and Hereinafter, a structure of the pixel P in the display area DA, the dam, the buffer layer, and the auxiliary buffer layeraccording to the eighth embodiment of the present disclosure will be described in detail with reference to.

30 FIG. 29 FIG. 120 is a cross-sectional view illustrating an example of each of the damand the buffer layer in the non-display area NDA and the pixel P in the display area DA illustrated in.

30 FIG. 210 280 111 Referring to, in a display area DA, a TFTand a light emitting devicecan be provided on one surface of a first substrate.

231 111 210 111 A buffer layercan be provided on the first substrate, for protecting the TFTfrom water penetrating through the first substratevulnerable to penetration of water.

210 211 212 213 214 210 212 211 210 212 211 212 211 30 FIG. The TFTcan include an active layer, a gate electrode, a source electrode, and a drain electrode. In, the TFTare exemplarily illustrated as being provided as a top gate type where the gate electrodeis disposed on the active layer, but is not limited thereto. That is, the TFTcan be provided as a bottom gate type where the gate electrodeis disposed under the active layeror a double gate type where the gate electrodeis disposed both on and under the active layer.

211 231 111 211 211 111 The active layercan be formed on a buffer layerof the first substrate. The active layercan be formed of a silicon-based semiconductor material, an oxide-based semiconductor material, and/or the like. A light blocking layer for blocking external light incident on the active layercan be formed on the first substrate.

230 211 230 A gate insulation layercan be provided on the active layer. The gate insulation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof. However, the present embodiment is not limited thereto.

212 230 212 The gate electrodecan be provided on the gate insulation layer. The gate electrodecan be formed of a single layer or a multilayer which includes one of Mo, Al, Cr, (Au, Ti, Ni, Nd, and Cu, or an alloy thereof, but is not limited thereto.

240 212 240 An interlayer insulation layercan be provided on the gate electrode. The interlayer insulation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof.

213 214 240 213 211 220 230 214 211 220 230 213 214 The source electrodeand the drain electrodecan be provided on the interlayer insulation layer. The source electrodecan be connected to the active layerthrough a contact hole which passes through the gate insulation layerand the interlayer insulation layer, and the drain electrodecan be connected to the active layerthrough another contact hole which passes through the gate insulation layerand the interlayer insulation layer. The source electrodeand the drain electrodecan each be formed of a single layer or a multilayer which includes one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof, but are not limited thereto.

250 210 250 250 A passivation layercan be provided on the TFT. The passivation layercan act as an insulation layer. The passivation layercan be formed of an inorganic layer, and for example, can be formed of SiOx, SiNx, or a multilayer thereof.

261 210 250 261 A first planarization layerfor planarizing a step height caused by the TFTcan be provided on the passivation layer. The first planarization layercan be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

215 214 281 261 215 214 261 250 215 An auxiliary electrodefor electrically connecting the drain electrodeto the second electrodecan be provided on the first planarization layer. The auxiliary electrodecan be connected to the drain electrodethrough a contact hole which passes through the first planarization layerand the passivation layer. The auxiliary electrodecan be formed of a single layer or a multilayer which includes one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof, but is not limited thereto.

262 215 262 A second planarization layercan be provided on the auxiliary electrode. The second planarization layercan be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

280 284 262 280 282 283 281 282 281 282 283 281 A light emitting deviceand a bankcan be provided on the second planarization layer. The light emitting devicecan include a first electrode, a light emitting layer, and a second electrode. The first electrodecan be a cathode electrode, and the second electrodecan be an anode electrode. An area where the first electrode, the light emitting layer, and the second electrodeare stacked can be defined as an emissive area EA.

281 262 281 214 210 262 281 The second electrodecan be provided on the second planarization layer. The second electrodecan be connected to the drain electrodeof the TFTthrough a contact hole which passes through the second planarization layer. The second electrodecan be formed of a metal material, which is high in reflectivity, such as a stacked structure (Ti/Al/Ti) of Al and Ti, a stacked structure (ITO/Al/ITO) of Al and ITO, an APC alloy, or a stacked structure (ITO/APC/ITO) of an APC alloy and ITO. The APC alloy can be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

284 262 281 284 The bankcan be provided on the second planarization layerto cover an edge of the second electrode, for dividing a plurality of emissive areas EA. The bankcan be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

285 284 285 284 284 A spacercan be provided on the bank. The spacercan be formed of the same material as that of the bank, or can be formed of a material which differs from that of the bank.

283 281 284 285 283 281 282 The light emitting layercan be provided on the second electrode, the bank, and the spacer. The light emitting layercan include a hole transporting layer, at least one light emitting layer, and an electron transporting layer. In this case, when a voltage is applied to the second electrodeand the first electrode, a hole and an electron can move to the light emitting layer through the hole transporting layer and the electron transporting layer and can be combined with each other in the light emitting layer to emit light.

282 283 282 282 The first electrodecan be provided on the light emitting layer. When an electroluminescence display apparatus is implemented in a top emission structure, the first electrodecan be formed of a transparent conductive material (or TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO) capable of transmitting light, or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag. A capping layer can be provided on the first electrode.

290 280 290 283 282 290 An encapsulation layercan be provided on the light emitting device. The encapsulation layerprevents oxygen or water from penetrating into the light emitting layerand the first electrode. To this end, the encapsulation layercan include at least one inorganic layer and at least one organic layer.

290 291 292 293 291 282 292 291 292 283 282 291 293 292 For example, the encapsulation layercan include a first inorganic layer, an organic layer, and a second inorganic layer. In this case, the first inorganic layercan be provided to cover the first electrode. The organic layercan be provided on the first inorganic layer. The organic layercan be provided to have a sufficient thickness, for preventing particles from penetrating into the light emitting layerand the first electrodevia the first inorganic layer. The second inorganic layercan be provided to cover the organic layer.

30 FIG. 290 120 130 111 Referring to, the non-display area NDA can include the encapsulation layer, the dam, and the buffer layerprovided on one surface of the first substrate.

290 280 280 290 290 291 292 293 291 282 292 291 293 292 The encapsulation layercan be provided to cover the light emitting deviceprovided in the display area DA and can prevent oxygen or water from penetrating into the light emitting device. The encapsulation layercan include at least one inorganic layer and at least one organic layer. For example, the encapsulation layercan include a first inorganic layer, an organic layer, and a second inorganic layer. In this case, the first inorganic layercan be provided to cover the first electrode, the organic layercan be provided on the first inorganic layer, and the second inorganic layercan be provided to cover the organic layer.

291 293 291 293 The first and second inorganic layersandcan each be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto. The first and second inorganic layersandcan be deposited through a CVD process or an ALD process, but are not limited thereto.

292 283 292 283 292 292 The organic layercan be formed of a transparent material, for transmitting light emitted from the light emitting layer. The organic layercan be formed of an organic material (for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin) capable of transmitting 99% or more of the light emitted from the light emitting layer. The organic layercan be formed through a vapor deposition process, a printing process, or a slit coating process, which uses an organic material, but is not limited thereto. In other embodiments, the organic layercan be formed through an ink-jet process.

120 292 290 292 290 292 293 292 292 292 293 120 292 292 The damcan be provided to surround an outer portion of the display area DA and can block a flow of the organic layerconfiguring the encapsulation layer. The organic layerconfiguring the encapsulation layeris good in coverage performance, but is low in barrier performance. Therefore, the organic layercan be encapsulated by the second inorganic layer. However, if the organic layerflows into a region where the organic layeris to be formed, water or oxygen penetrates into the inside through the organic layerwhich is exposed without being encapsulated by the second inorganic layer. In order to solve such a problem, the damcan block a flow of the organic layer, thereby preventing the organic layerfrom being exposed at the outside of the display apparatus.

120 292 292 290 292 290 292 120 292 290 292 Moreover, the damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring the encapsulation layerdoes not flow into the pad area PA. When the organic layerconfiguring the encapsulation layerpenetrates into the pad area PA, an electrical contact is not normally made in a pad due to the organic layer, and for this reason, a driving error or a lighting test error occurs. In order to solve such a problem, the damcan block a flow of the organic layerconfiguring the encapsulation layer, thereby preventing the organic layerfrom penetrating into the pad area PA.

30 FIG. 120 122 121 122 122 121 122 122 122 292 290 292 122 121 122 292 As illustrated in, the damcan include a first damand a second damspaced apart from the first dam. The first damcan be provided in the non-display area NDA to surround an outer region of the display area DA, and the second damcan be spaced apart from the first damand can be disposed to surround the first dam. The first damcan block a flow of the organic layerconfiguring the encapsulation layer. When the organic layerflows out to an outer portion of the first dam, the second damspaced apart from the first damcan block a flow of the organic layer.

122 121 262 284 285 122 121 262 284 285 122 121 121 122 121 122 121 122 122 121 262 284 285 121 122 122 121 262 121 122 121 122 122 121 284 121 122 121 122 122 121 285 122 284 285 121 262 284 285 122 284 121 262 284 30 FIG. The first damand the second damcan each be formed of a single layer including the same material as that of at least one of the second planarization layer, the bank, and the spacerof the pixel P. Also, the first damand the second damcan each be formed of a multilayer including the same materials as those of two or more of the second planarization layer, the bank, and the spacerof the pixel P. For example, as illustrated in, when each of the first damand the second damis formed of a triple layer including a plurality of lower layersc andc, a plurality of intermediate layersb andb, and a plurality of upper layersa anda, the first damand the second damcan each be formed of the same materials as those of the second planarization layer, the bank, and the spacerof the pixel P. The lower layersc andc of each of the first damand the second damcan each be formed of the same material as that of the second planarization layerof the pixel P. The intermediate layersb andb, disposed on the lower layersc andc, of each of the first damand the second damcan each be formed of the same material as that of the bankof the pixel P. Also, the upper layersa anda, disposed on the intermediate layersb andb, of each of the first damand the second damcan each be formed of the same material as that of the spacerof the pixel P. However, the present embodiment is not limited thereto. For example, the first damcan be formed of the same materials as those of the bankand the spacerof the pixel P, and the second damcan be formed of the same materials as those of the second planarization layer, the bank, and the spacerof the pixel P. Alternatively, the first damcan be formed of the same material as that of the bankof the pixel P, and the second damcan be formed of the same materials as those of the second planarization layerand the bankof the pixel P.

130 120 130 111 291 293 130 130 The buffer layercan be disposed in the non-display area NDA and can be spaced apart from the dam. The buffer layercan support a mask so as to maintain a certain distance between the mask and the first substratewhen performing a process of depositing the first inorganic layeror the second inorganic layer. To this end, the mask can be disposed on the buffer layerto contact the buffer layer.

29 30 FIGS.and 130 130 121 120 291 293 1 2 130 As illustrated in, the buffer layercan be disposed between the pad area PA and the display area DA. For example, the buffer layercan be formed between the second damof the damand the pad area PA to prevent the first inorganic layeror the second inorganic layerfrom being formed in the pad area PA. Also, a plurality of lines VALand VALwhich electrically connect the pad PAD in the pad area PA to the pixel P in the display area DA can be protected from static electricity by the buffer layer.

30 FIG. 130 136 138 136 138 120 136 1 Referring to, the buffer layercan include a first buffer layerand a second buffer layer. The first buffer layerand the second buffer layercan be disposed between the pad area PA and the dam. Also, the first buffer layercan be disposed on a first power auxiliary line VAL, to which a source voltage is applied from the pad PAD in the pad area PA, and a first data link line to which a data signal is applied from the pad PAD.

1 111 136 1 1 213 214 250 1 250 1 Here, the first power auxiliary line VALor the first data link line can be provided on the first substrate. Also, the first buffer layercan be disposed on the first power auxiliary line VALor the first data link line. The first power auxiliary line VALand the first data link line can each be formed of the same material as that of the source electrodeand the drain electrodeof the pixel P. Also, the passivation layercan be disposed between the first power auxiliary line VAL, the first data link line, and the first buffer layer, and the passivation layercan be provided to surround both side surfaces and a top of each of the first power auxiliary line VALand the first data link line.

2 136 2 215 2 136 A second power auxiliary line VALor a second data link line can be provided on the first buffer layer, and the second power auxiliary line VALand the second data link line can each be formed of the same material as that of the auxiliary electrodeof the pixel P. The second power auxiliary line VALcan be connected to the second data link line through a contact hole passing through the first buffer layer.

138 2 The second buffer layercan be disposed on the second power auxiliary line VAL, to which the source voltage is applied from the pad PAD in the pad area PA, and the second data link line to which the data signal is applied from the pad PAD.

291 292 290 138 The first inorganic layerand the second inorganic layerconfiguring the encapsulation layercan be provided to cover a portion of a top of the second buffer layer.

1 2 130 130 290 The first power auxiliary line VAL, the second power auxiliary line VAL, the first data link line, and the second data link line which electrically connect the pad PAD in the pad area PA to the pixel P in the display area DA can be protected from static electricity by the buffer layer. For example, the buffer layerprevents arcing from occurring in a process of forming the encapsulation layer.

180 120 180 31 FIG. 31 FIG. 29 FIG. 31 FIG. 29 FIG. 30 FIG. The auxiliary buffer layeraccording to the eighth embodiment of the present disclosure will be described below in detail with reference to.is a cross-sectional view taken along line II-II′ of.is a cross-sectional view illustrating an example of the damand the auxiliary buffer layerin the display area DA of. Hereinafter, descriptions of the same elements as those ofare omitted or will be briefly given.

31 FIG. 29 FIG. 122 121 120 122 121 122 121 122 122 122 292 290 292 122 121 122 292 Referring to, a first damand a second damconfiguring a damcan be disposed in a non-display area NDA. As illustrated in, the first damand the second damcan be disposed in the non-display area NDA and can be spaced apart from a display area DA. The first damcan be provided in the non-display area NDA to surround an outer region of the display area DA, and the second damcan be spaced apart from the first damand can be provided to surround the first dam. The first damcan block a flow of an organic layerconfiguring an encapsulation layer. When the organic layerflows out to an outer portion of the first dam, the second damspaced apart from the first damcan block a flow of the organic layer.

1 240 2 1 250 250 2 122 122 3 262 2 2 122 261 262 3 122 122 A first power auxiliary line VALcan be provided on an interlayer insulation layer, on a side surface of the display area DA. A second power auxiliary line VALcan be connected to the first power auxiliary line VAL, disposed under a passivation layer, through a contact hole passing through the passivation layer. The second power auxiliary line VALcan be provided to overlap a lower surface of a lower layera of the first dam. A third power auxiliary line VALprovided on a second planarization layercan be connected to the second power auxiliary line VALthrough an opening which exposes the second power auxiliary line VAL, in a region between the first damand an end of each of a first planarization layerand the second planarization layer. The third power auxiliary line VALcan be provided to overlap an upper surface of the lower layera of the first dam.

1 213 214 2 215 3 291 The first power auxiliary line VALcan be formed of the same material as that of a source electrodeand a drain electrodeof a pixel P. The second power auxiliary line VALcan be formed of the same material as that of an auxiliary electrodeof the pixel P. The third power auxiliary line VALcan be formed of the same material as that of a second electrodeof the pixel P.

180 121 120 180 111 291 293 180 180 An auxiliary buffer layercan be disposed in the non-display area NDA and can be spaced apart from the second damof the dam. The auxiliary buffer layercan support a mask so as to maintain a certain distance between the mask and a first substratewhen performing a process of depositing a first inorganic layeror a second inorganic layer. To this end, the mask can be disposed on the auxiliary buffer layerto contact the auxiliary buffer layer.

291 292 180 291 292 111 180 291 293 180 120 180 180 180 291 293 180 291 292 180 180 When the first inorganic layeror the second inorganic layeris deposited after the mask is disposed on the auxiliary buffer layer, the first inorganic layeror the second inorganic layercan be provided in a region other than a region where the mask is disposed. For example, since a space is not formed between the mask and the first substrateby the auxiliary buffer layer, the first inorganic layeror the second inorganic layeris prevented from penetrating into the region where the mask is disposed. Therefore, in the present embodiment, since the auxiliary buffer layeris disposed between the damand a scribing line SL and the mask is disposed on a second buffer layerb of the auxiliary buffer layerto contact the second auxiliary buffer layerb, the first inorganic layeror the second inorganic layeris prevented from being formed in an outer portion (for example, the scribing line SL) of the auxiliary buffer layer. Therefore, the first inorganic layerand the second inorganic layercan be provided to partially overlap a top of the second auxiliary buffer layerb of the auxiliary buffer layer.

29 FIG. 180 180 130 122 121 122 121 130 121 180 130 121 122 180 130 As illustrated in, the auxiliary buffer layercan be disposed to surround at least three surfaces of the display area DA. For example, the auxiliary buffer layercan be disposed to three surfaces of the display area DA except one surface, on which the buffer layeris provided, of the display area DA. Therefore, the first damcan be disposed in the non-display area NDA to surround the display area DA. Also, the second damcan be spaced apart from the first damand can be disposed to surround the first dam. Also, the buffer layercan be disposed between the second damand a pad area PA to face one of four surfaces of the display area DA. The auxiliary buffer layercan be disposed to face three surfaces other than the one surface of the display area DA facing the buffer layer. Accordingly, three of four surfaces of the second damwhich is provided to surround the first damcan be disposed between the display area DA and the auxiliary buffer layer. Also, the other one surface can be disposed between the display area DA and the buffer layer.

31 FIG. 180 180 250 180 180 Referring to, the auxiliary buffer layercan include a first auxiliary buffer layera disposed on the passivation layerand the second auxiliary buffer layerb disposed on the first auxiliary buffer layera.

180 284 180 285 The first auxiliary buffer layera can be formed of the same material as that of a bankof the pixel P. Also, the second auxiliary buffer layerb can be formed of the same material as that of a spacerof the pixel P.

180 180 180 111 180 180 250 240 230 231 Moreover, when both side surfaces of a display apparatus are bent, a crack occurs in the auxiliary buffer layer. In order to prevent the crack from propagating to the display area DA, a groove can be formed by patterning the first auxiliary buffer layera and the second auxiliary buffer layerb. For example, the groove which exposes the first substratecan be formed by removing the second auxiliary buffer layerb, the first auxiliary buffer layera, the passivation layer, an interlayer insulation layer, a gate insulation layer, and a buffer layer. The groove can be referred to as a crack prevention groove.

32 FIG. 33 FIG. 32 FIG. is a plan view illustrating a first substrate of a display apparatus according to a ninth embodiment of the present disclosure.is a cross-sectional view taken along line IV-IV′ of.

32 33 FIGS.to 111 Referring to, the first substratecan be divided into a display area DA and a non-display area NDA.

A plurality of pixels P for displaying an image can be provided in the display area DA. Each of the pixels P can include a TFT and a light emitting device. When a gate signal is input through a corresponding gate line by using the TFT, each of the pixels P can supply a current to the light emitting device with a data voltage of a corresponding data line. Therefore, the light emitting device of each pixel P can emit light having certain brightness, based on the current.

120 180 1 310 A pad area PA where a plurality of pads PAD are provided, a dam, an auxiliary buffer layer, a first power auxiliary line VAL, and a crack detection linecan be provided in the non-display area NDA.

111 A pad area PA can be disposed in one edge of the first substrate. The pad area PA can include the plurality of pads PAD, and the plurality of pads PAD can be electrically connected to a flexible film by an anisotropic conductive film.

120 122 121 122 121 122 121 292 122 121 292 292 290 The damcan include a first damand a second dam. The first damand the second damcan be disposed to surround the display area DA, and at least one of the first damand the second damcan block a flow of an organic layer. Also, the first damand the second damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring an encapsulation layerof a pixel P does not penetrate into the pad area PA.

180 180 120 120 291 292 290 The auxiliary buffer layercan be disposed in the non-display area NDA and can be spaced apart from the display area DA. For example, the auxiliary buffer layercan be spaced apart from the second damof the damin the non-display area NDA and can support a mask device which is used to form a first inorganic layeror a second inorganic layerconfiguring the encapsulation layer.

1 180 1 120 180 1 1 120 180 120 The first power auxiliary line VALcan be provided in the non-display area NDA and can be disposed between the display area DA and the auxiliary buffer layer. For example, the first power auxiliary line VALcan be disposed between the damand the auxiliary buffer layerin the non-display area NDA. Also, the first power auxiliary line VALcan be electrically connected to the pad PAD in the pad area PA and can stably supply power to a display panel PNL. Also, the first power auxiliary line VALprovided between the damand the auxiliary buffer layercan be provided to extend to a lower region of the dam.

310 1 310 1 180 310 310 310 The crack detection linecan be disposed in the non-display area NDA and can be spaced apart from the first power auxiliary line VAL. For example, the crack detection linecan be disposed between the first power auxiliary line VALand the auxiliary buffer layerin the non-display area NDA. Also, the crack detection linecan be electrically connected to the pad PAD in the pad area PA. Also, when a crack occurs in the non-display area NDA, the crack detection lineis damaged. A resistance of the damaged crack detection linecan increase, and thus, the occurrence of the crack can be sensed.

120 180 1 310 33 FIG. Hereinafter, the dam, the auxiliary buffer layer, the first power auxiliary line VAL, and the crack detection lineaccording to the ninth embodiment of the present disclosure will be described in detail with reference to.

33 FIG. 290 120 180 1 310 111 Referring to, an encapsulation layer, a dam, an auxiliary buffer layer, a first power auxiliary line VAL, and a crack detection lineprovided on a first substratecan be provided in a non-display area NDA.

290 280 280 290 290 291 292 293 291 282 292 291 293 292 The encapsulation layercan be provided to cover the light emitting deviceprovided in the display area DA and can prevent oxygen or water from penetrating into the light emitting device. The encapsulation layercan include at least one inorganic layer and at least one organic layer. For example, the encapsulation layercan include a first inorganic layer, an organic layer, and a second inorganic layer. In this case, the first inorganic layercan be provided to cover the first electrode, the organic layercan be provided on the first inorganic layer, and the second inorganic layercan be provided to cover the organic layer.

291 293 The first and second inorganic layersandcan each be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, but are not limited thereto.

292 The organic layercan be formed of acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

120 292 290 292 290 292 293 292 292 292 293 120 292 292 The damcan be provided to surround an outer portion of the display area DA and can block a flow of the organic layerconfiguring the encapsulation layer. The organic layerconfiguring the encapsulation layeris good in coverage performance, but is low in barrier performance. Therefore, the organic layercan be encapsulated by the second inorganic layer. However, if the organic layerflows into a region where the organic layeris to be formed, water or oxygen penetrates into the inside through the organic layerwhich is exposed without being encapsulated by the second inorganic layer. In order to solve such a problem, the damcan block a flow of the organic layer, thereby preventing the organic layerfrom being exposed at the outside of the display apparatus.

120 292 292 290 292 290 292 120 292 290 292 Moreover, the damcan be disposed between the display area DA and the pad area PA and can block a flow of the organic layerso that the organic layerconfiguring the encapsulation layerdoes not flow into the pad area PA. When the organic layerconfiguring the encapsulation layerpenetrates into the pad area PA, an electrical contact is not normally made in a pad due to the organic layer, and for this reason, a driving error or a lighting test error occurs. In order to solve such a problem, the damcan block a flow of the organic layerconfiguring the encapsulation layer, thereby preventing the organic layerfrom penetrating into the pad area PA.

33 FIG. 120 122 121 122 122 121 122 122 122 292 290 292 122 121 122 292 As illustrated in, the damcan include a first damand a second damspaced apart from the first dam. The first damcan be provided in the non-display area NDA to surround an outer region of the display area DA, and the second damcan be spaced apart from the first damand can be disposed to surround the first dam. The first damcan block a flow of the organic layerconfiguring the encapsulation layer. When the organic layerflows out to an outer portion of the first dam, the second damspaced apart from the first damcan block a flow of the organic layer.

122 121 262 284 285 122 121 262 284 285 122 121 121 122 121 122 121 122 122 121 262 284 285 121 122 122 121 262 121 122 121 122 122 121 284 121 122 121 122 122 121 285 122 284 285 121 262 284 285 122 284 121 262 284 33 FIG. The first damand the second damcan each be formed of a single layer including the same material as that of at least one of a second planarization layer, a bank, and a spacerof a pixel P. Also, the first damand the second damcan each be formed of a multilayer including the same materials as those of two or more of the second planarization layer, the bank, and the spacerof the pixel P. For example, as illustrated in, when each of the first damand the second damis formed of a triple layer including a plurality of lower layersc andc, a plurality of intermediate layersb andb, and a plurality of upper layersa anda, the first damand the second damcan each be formed of the same materials as those of the second planarization layer, the bank, and the spacerof the pixel P. The lower layersc andc of each of the first damand the second damcan each be formed of the same material as that of the second planarization layerof the pixel P. The intermediate layersb andb, disposed on the lower layersc andc, of each of the first damand the second damcan each be formed of the same material as that of the bankof the pixel P. Also, the upper layersa anda, disposed on the intermediate layersb andb, of each of the first damand the second damcan each be formed of the same material as that of the spacerof the pixel P. However, the present embodiment is not limited thereto. For example, the first damcan be formed of the same materials as those of the bankand the spacerof the pixel P, and the second damcan be formed of the same materials as those of the second planarization layer, the bank, and the spacerof the pixel P. Alternatively, the first damcan be formed of the same material as that of the bankof the pixel P, and the second damcan be formed of the same materials as those of the second planarization layerand the bankof the pixel P.

1 180 1 1 240 1 250 1 1 120 250 1 120 180 120 250 33 FIG. The first power auxiliary line VALcan be disposed between the display area DA and the auxiliary buffer layer. The first power auxiliary line VALcan be electrically connected to a pad PAD in the pad area PA and can stably supply power to a display panel PNL. Also, the first power auxiliary line VALcan be provided on an interlayer insulation layer. Also, the first power auxiliary line VALcan be provided under a passivation layer. Also, the first power auxiliary line VALcan be formed of the same material as that of a source electrode and a drain electrode of a TFT. Therefore, the first power auxiliary line VALcan be disposed under the damprovided on the passivation layer. For example, as illustrated in, the first power auxiliary line VALprovided between the damand the auxiliary buffer layercan be provided to extend to a lower region of the damprovided on the passivation layer.

2 1 250 2 1 250 250 2 122 122 A second power auxiliary line VALcan be further provided on the first power auxiliary line VALwith the passivation layertherebetween. The second power auxiliary line VALcan be connected to the first power auxiliary line VAL, disposed under the passivation layer, through a contact hole passing through the passivation layer. The second power auxiliary line VALcan be provided to overlap a lower surface of the lower layera of the first dam.

3 262 3 262 2 2 122 261 262 3 122 122 A third power auxiliary line VALcan be further provided on a second planarization layer. The third power auxiliary line VALprovided on the second planarization layercan be connected to the second power auxiliary line VALthrough an opening which exposes the second power auxiliary line VAL, in a region between the first damand an end of each of a first planarization layerand the second planarization layer. The third power auxiliary line VALcan be provided to overlap an upper surface of the lower layera of the first dam.

1 240 2 261 3 262 The first power auxiliary line VALcan be formed of the same material as that of an electrode provided on the interlayer insulation layerin the pixel P. The second power auxiliary line VALcan be formed of the same material as that of an electrode provided on the first planarization layerin the pixel P. The third power auxiliary line VALcan be formed of the same material as that of an electrode provided on the second planarization layerin the pixel P.

180 1 180 111 291 293 180 180 The auxiliary buffer layercan be disposed in the non-display area NDA and can be spaced apart from the first power auxiliary line VAL. The auxiliary buffer layercan support a mask so as to maintain a certain distance between the mask and the first substratewhen performing a process of depositing the first inorganic layeror the second inorganic layer. To this end, the mask can be disposed on the auxiliary buffer layerto contact the auxiliary buffer layer.

291 292 180 291 292 111 180 291 293 180 120 180 180 180 291 293 180 291 292 180 180 When the first inorganic layeror the second inorganic layeris deposited after the mask is disposed on the auxiliary buffer layer, the first inorganic layeror the second inorganic layercan be provided in a region other than a region where the mask is disposed. For example, since a space is not formed between the mask and the first substrateby the auxiliary buffer layer, the first inorganic layeror the second inorganic layeris prevented from penetrating into the region where the mask is disposed. Therefore, in the present embodiment, since the auxiliary buffer layeris disposed between the damand a scribing line SL and the mask is disposed on a second buffer layerb of the auxiliary buffer layerto contact the second auxiliary buffer layerb, the first inorganic layeror the second inorganic layeris prevented from being formed in an outer portion (for example, the scribing line SL) of the auxiliary buffer layer. Therefore, the first inorganic layerand the second inorganic layercan be provided to partially overlap a top of the second auxiliary buffer layerb of the auxiliary buffer layer.

33 FIG. 180 180 250 180 180 Referring to, the auxiliary buffer layercan include a first auxiliary buffer layera disposed on the passivation layerand the second auxiliary buffer layerb disposed on the first auxiliary buffer layera.

180 284 180 285 The first auxiliary buffer layera can be formed of the same material as that of the bankof the pixel P. Also, the second auxiliary buffer layerb can be formed of the same material as that of the spacerof the pixel P.

180 180 180 111 180 180 250 240 230 231 Moreover, when both side surfaces of a display apparatus are bent, a crack occurs in the auxiliary buffer layer. In order to prevent the crack from propagating to the display area DA, a groove can be formed by patterning the first auxiliary buffer layera and the second auxiliary buffer layerb. For example, the groove which exposes the first substratecan be formed by removing the second auxiliary buffer layerb, the first auxiliary buffer layera, the passivation layer, the interlayer insulation layer, a gate insulation layer, and a buffer layer. The groove can be referred to as a crack prevention groove.

310 1 310 1 180 310 310 310 The crack detection linecan be disposed in the non-display area NDA and can be spaced apart from the first power auxiliary line VAL. For example, the crack detection linecan be disposed between the first power auxiliary line VALand the auxiliary buffer layerin the non-display area NDA. Also, the crack detection linecan be electrically connected to the pad PAD in the pad area PA. Also, when both side surfaces of a display apparatus are bent, a crack occurs in the non-display area NDA. In this manner when the crack occurs in the non-display area NDA, the crack detection lineis damaged. A resistance of the damaged crack detection linecan increase, and thus, the occurrence of the crack can be sensed.

310 230 310 230 310 210 The crack detection linecan be provided on the gate insulation layer. Also, the crack detection linecan be formed of the same material as that of an electrode provided on the gate insulation layerin the pixel P. For example, the crack detection linecan be formed of the same material as that of a gate electrode of a TFT. A current based on a reference voltage can flow through the crack detection line, and then, an output voltage can be detected. Subsequently, whether the detected output voltage is within a reference voltage range can be determined based on a detection result signal, thereby determining whether the display panel is damaged or not.

180 310 291 293 290 310 291 293 The auxiliary buffer layercan be provided to overlap the crack detection line. Static electricity can occur in a process of depositing the first inorganic layeror the second inorganic layerconfiguring the encapsulation layer. Therefore, the damage of the crack detection linecaused by the static electricity occurring in the process of depositing the first inorganic layeror the second inorganic layeris reduced.

One or more embodiments of the present disclosure will be described below.

A display apparatus according to an embodiment of the present disclosure includes a substrate including a display area where a plurality of pixels are provided and a non-display area surrounding the display area, an encapsulation layer including an inorganic layer and an organic layer and covering the display area, a dam disposed in the non-display area to surround the display area and to block a flow of the organic layer, a pad disposed in one edge of the non-display area and spaced apart from the dam in the non-display area, an auxiliary buffer layer spaced apart from the dam and disposed in the non-display area to overlap an end of the inorganic layer, a power auxiliary line disposed between the dam and the auxiliary buffer layer and electrically connected to the pad to receive a voltage from the pad, and a crack detection line spaced apart from the power auxiliary line and electrically connected to the pad.

According to an embodiment of the present disclosure, the encapsulation layer can include a first inorganic layer covering the display area, an organic layer provided on the first inorganic layer, and a second inorganic layer covering the organic layer, and the auxiliary buffer layer can contact an end of at least one of the first inorganic layer and the second inorganic layer.

According to an embodiment of the present disclosure, the first inorganic layer and the second inorganic layer can cover a portion of a top of the auxiliary buffer layer.

According to an embodiment of the present disclosure, the auxiliary buffer layer can be disposed to overlap the crack detection line.

According to an embodiment of the present disclosure, the auxiliary buffer layer can further include a crack prevention groove.

According to an embodiment of the present disclosure, the auxiliary buffer layer can include an organic material.

According to an embodiment of the present disclosure, the auxiliary buffer layer can include a first auxiliary buffer layer and a second auxiliary buffer layer on the first auxiliary buffer layer.

According to an embodiment of the present disclosure, the first auxiliary buffer layer can include the same material as a material of a bank of a pixel, and the second auxiliary buffer layer can include the same material as a material of a spacer of the pixel.

According to an embodiment of the present disclosure, the crack detection line can include the same material as a material of a gate electrode of a pixel.

According to an embodiment of the present disclosure, the power auxiliary line can include the same material as a material of each of a source electrode and a drain electrode of a pixel.

According to an embodiment of the present disclosure, the power auxiliary line can be disposed to extend to a lower region of the dam.

A display apparatus according to an embodiment of the present disclosure, includes a substrate including a display area where a plurality of pixels are provided and a non-display area adjacent to the display area, a pad disposed in one edge of the non-display area, a dam disposed in the non-display area to surround the display area and disposed between the display area and the pad in the non-display area where the pad is disposed, an auxiliary buffer layer disposed in the non-display area and spaced apart from the dam, a power auxiliary line disposed between the display area and the auxiliary buffer layer and electrically connected to the pad, and a crack detection line provided to overlap a bottom of the auxiliary buffer layer and electrically connected to the pad.

According to an embodiment of the present disclosure, the power auxiliary line can extend to overlap the dam.

According to an embodiment of the present disclosure, the auxiliary buffer layer can be disposed on the crack detection line.

According to an embodiment of the present disclosure, the crack detection line can be spaced apart from the power auxiliary line.

According to an embodiment of the present disclosure, the crack detection line can be disposed to surround at least three surfaces of the display area.

According to an embodiment of the present disclosure, the power auxiliary line can be disposed between the display area and the crack detection line.

As described above, according to the embodiments of the present disclosure, since the buffer layer is provided between the non-display area and the scribing line and the mask is disposed on the buffer layer when depositing an inorganic layer, the inorganic layer is not provided on the scribing line. Thus, a crack is prevented from occurring in the inorganic layer in the scribing process, thereby enhancing a yield rate and reliability of the display apparatus.

Moreover, according to the embodiments of the present disclosure, since the buffer layer is provided in the non-display area, penetration of water, oxygen, and other materials via the side surface of the display apparatus is minimized, thereby enhancing the lifetime and reliability of the display apparatus.

Moreover, according to the embodiments of the present disclosure, since the buffer layer is provided higher in height than the dam, the damage of the dam is minimized when disposing the mask on the buffer layer. Accordingly, water, oxygen and other materials are prevented from being propagated to an organic layer via the damaged dam.

Moreover, according to the embodiments of the present disclosure, since the buffer layer is provided in a plurality of island type patterns, an increase in stress caused by forming of the buffer layer is minimized in the non-display area.

Moreover, according to the embodiments of the present disclosure, since the buffer layer is provided not to overlap an electrode, the damage of the electrode is minimized when disposing the mask on the buffer layer. Accordingly, any occurrence of a defect caused by the damaged electrode can be prevented.

Moreover, according to the embodiments of the present disclosure, since the first buffer layer and the second buffer layer are provided, the first inorganic layer and the second inorganic layer can be provided to have different areas, and thus, the second inorganic layer can fully cover the first inorganic layer and the organic layer, thereby preventing penetration of oxygen and water.

Moreover, according to the embodiments of the present disclosure, since the buffer layer is formed of the same material as that of at least one of the planarization layer and the bank, it is not required to add a separate manufacturing process, which simplifies the process with reduced cost.

Moreover, according to the embodiments of the present disclosure, the buffer layer can be provided on the power auxiliary line through which the source voltage is supplied to the power line, and thus, even when a lot of electric charges instantaneously concentrate on the edge of the mask in the process of depositing the first inorganic layer or the second inorganic layer, the buffer layer prevents static electricity from occurring between the mask and the power auxiliary line.

Moreover, according to the embodiments of the present disclosure, since the at least one groove exposing the passivation layer is provided on the buffer layer, water and oxygen which can flow in from the outside are prevented from being propagated to the inside.

Moreover, according to the embodiments of the present disclosure, since the second power auxiliary line is additionally provided on the first power auxiliary line by using the buffer layer, a cross-sectional area of the power auxiliary line increases, and thus, a resistance is reduced, thereby enabling the source voltage to be stably supplied.

Moreover, according to the embodiments of the present disclosure, the crack detection line can be provided in the outer region of the display panel to detect a crack which may occur in the outer region of the display panel, thereby decreasing an error rate of the display apparatus.

Moreover, according to the embodiments of the present disclosure, the organic layer can be provided to overlap the crack detection line provided in the outer region of the display panel, thereby reducing the damage of the crack detection line, which can be caused by static electricity that can be generated in the process of depositing the encapsulation layer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosures. Thus, it is intended that the present disclosure covers the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.