Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A transistor structure, comprising: a III-V heterostructure comprising a first III-V compound semiconductor material in contact with a second III-V compound semiconductor material; a gate stack over a channel region of the first III-V compound semiconductor material, wherein the gate stack comprises a gate electrode separated from the channel region by a gate dielectric; and a source region and a drain region electrically coupled to opposite ends of the channel region through a tip region in the first III-V compound semiconductor material, the tip region in contact with a sub-tip region of the second III-V compound semiconductor material, wherein both the tip region and sub-tip region comprise an amphoteric dopant, which activates as a donor within the first III-V compound semiconductor material, and as an acceptor within the second III-V compound semiconductor material.
This invention relates to a transistor structure utilizing a III-V heterostructure to improve device performance. The problem addressed is the difficulty in achieving efficient doping in III-V semiconductor materials, which limits their use in high-performance transistors. The solution involves a heterostructure where a first III-V compound semiconductor material forms a channel region, and a second III-V compound semiconductor material is in contact with it. A gate stack, including a gate electrode and a gate dielectric, is positioned over the channel region to control current flow. The transistor includes source and drain regions connected to the channel through a tip region in the first III-V material, which interfaces with a sub-tip region in the second III-V material. Both the tip and sub-tip regions contain an amphoteric dopant that functions as a donor in the first material and as an acceptor in the second material. This dual-doping behavior enhances carrier mobility and reduces contact resistance, improving overall transistor efficiency. The design leverages the unique properties of III-V materials to create a high-performance transistor suitable for advanced electronic applications.
2. The transistor structure of claim 1 , wherein: a majority charge carrier in the channel region is an electron; and the second III-V compound semiconductor material has p-type conductivity.
This invention relates to a transistor structure incorporating III-V compound semiconductors, addressing challenges in high-performance electronic devices such as high electron mobility and efficient charge carrier control. The transistor includes a channel region composed of a first III-V compound semiconductor material, where the primary charge carriers in this region are electrons, enabling high-speed operation. A second III-V compound semiconductor material with p-type conductivity is integrated into the structure, likely serving as a gate or contact region to modulate the channel's conductivity. The combination of n-type channel and p-type material facilitates efficient switching and current control, which is critical for applications in high-frequency and low-power electronics. The use of III-V materials enhances electron mobility compared to traditional silicon-based transistors, making this structure suitable for advanced semiconductor devices. The p-type material may also improve interface properties and reduce leakage currents, further optimizing device performance. This design leverages the unique electronic properties of III-V compounds to achieve superior transistor characteristics, addressing limitations in conventional semiconductor technologies.
3. The transistor structure of claim 1 , wherein a sub-tip region of the second III-V compound semiconductor material comprises a same concentration of the amphoteric dopant as the tip region, the amphoteric dopant augmenting a p-n junction at the heterojunction of the first and second III-V compound semiconductor materials.
This invention relates to transistor structures incorporating III-V compound semiconductors, specifically addressing challenges in doping and junction formation. The structure includes a first III-V compound semiconductor material and a second III-V compound semiconductor material forming a heterojunction. A tip region of the second material is doped with an amphoteric dopant, which can act as either a donor or acceptor depending on the semiconductor's composition. The sub-tip region of the second material also contains the same concentration of this amphoteric dopant, enhancing the p-n junction at the heterojunction between the first and second materials. This doping strategy improves junction properties by ensuring consistent dopant distribution, which is critical for optimizing carrier transport and device performance. The amphoteric dopant's dual functionality allows for precise control over junction characteristics, addressing issues like leakage current and efficiency in III-V semiconductor devices. The invention is particularly useful in high-frequency and high-power applications where junction quality directly impacts performance.
4. The transistor structure of claim 1 , wherein the first III-V material is an alloy comprising any of InGaAs, InAs, GaAs, InP, or InSb.
This invention relates to a transistor structure incorporating a III-V semiconductor material, addressing challenges in high-performance electronic devices such as high electron mobility and compatibility with existing silicon-based fabrication processes. The transistor structure includes a channel region formed from a first III-V material, which is an alloy selected from InGaAs, InAs, GaAs, InP, or InSb. These materials are chosen for their superior electron mobility and bandgap properties, enabling faster switching speeds and improved efficiency in transistors. The structure may also include a second III-V material for additional layers, such as a barrier or buffer layer, to enhance carrier confinement and reduce leakage currents. The use of these specific III-V alloys allows for customization of electrical properties, such as bandgap and lattice constant, to optimize performance for different applications, including high-frequency and low-power electronics. The invention aims to leverage the advantages of III-V materials while maintaining compatibility with conventional semiconductor manufacturing techniques.
5. The transistor structure of claim 4 , wherein the second III-V material is an alloy comprising any of AlSb, InP, GaSb, GaAlSb, GaAsSb, InAlAs, GaAs, or AlGaAs.
This invention relates to semiconductor transistor structures, specifically those incorporating III-V compound materials to improve performance. The problem addressed is the need for high-speed, low-power transistors with enhanced carrier mobility and compatibility with existing semiconductor manufacturing processes. The invention describes a transistor structure with a channel region formed from a first III-V material and a second III-V material that is an alloy. The second III-V material is selected from a group including AlSb, InP, GaSb, GaAlSb, GaAsSb, InAlAs, GaAs, or AlGaAs. This alloy is used to optimize electrical properties such as bandgap, electron mobility, and lattice matching with the substrate or other layers. The transistor structure may include additional layers, such as a barrier layer or a buffer layer, to further enhance performance. The use of these specific III-V alloys allows for customization of the transistor's electrical characteristics, making it suitable for applications in high-frequency and high-efficiency electronic devices. The invention aims to provide a flexible design that can be tailored for different performance requirements while maintaining manufacturability.
6. The transistor structure of claim 1 , wherein the amphoteric dopant comprises one or more of Si, C, Ge, Sn, Te, Se, or O.
This invention relates to semiconductor transistor structures, specifically focusing on the use of amphoteric dopants to enhance device performance. The problem addressed is the need for improved doping techniques in transistors to achieve precise control over electrical properties, such as conductivity and threshold voltage, while minimizing defects and variability in semiconductor materials. The transistor structure incorporates an amphoteric dopant, which can exhibit both n-type and p-type doping behavior depending on the surrounding material and processing conditions. The amphoteric dopant includes elements such as silicon (Si), carbon (C), germanium (Ge), tin (Sn), tellurium (Te), selenium (Se), or oxygen (O). These dopants are strategically introduced into the semiconductor material to modulate its electrical characteristics. The amphoteric nature allows for flexible tuning of the transistor's properties, enabling optimization for specific applications. The doping process involves incorporating the amphoteric dopant into the semiconductor lattice, where it can act as either a donor or acceptor depending on the local environment. This dual functionality helps reduce defects and improve uniformity in the semiconductor material, leading to more reliable and efficient transistor operation. The use of these specific dopants also enhances compatibility with existing semiconductor manufacturing processes, ensuring scalability and cost-effectiveness. By leveraging amphoteric dopants, this invention provides a solution for achieving precise and stable doping in transistors, addressing challenges related to performance variability and defect formation in advanced semiconductor devices.
7. The transistor structure of claim 1 , wherein: the first III-V material comprises an alloy of two or more of: In, Ga, or As; and the amphoteric dopant comprises Si or C.
This invention relates to a transistor structure incorporating a III-V semiconductor material and an amphoteric dopant. The structure addresses challenges in semiconductor device fabrication, particularly in achieving precise doping control and performance optimization in III-V materials, which are critical for high-speed and low-power electronic applications. The transistor structure includes a first III-V material layer composed of an alloy containing two or more elements from indium (In), gallium (Ga), or arsenic (As). This alloy selection allows for tailored electronic properties, such as bandgap engineering and carrier mobility enhancement. The structure also incorporates an amphoteric dopant, which can be silicon (Si) or carbon (C). Amphoteric dopants can act as either n-type or p-type dopants depending on the semiconductor material and processing conditions, providing flexibility in device design and fabrication. The combination of the III-V alloy and the amphoteric dopant enables improved doping efficiency, reduced defect formation, and enhanced electrical performance. This design is particularly useful in advanced transistors, such as high-electron-mobility transistors (HEMTs) or field-effect transistors (FETs), where precise control over carrier concentration and mobility is essential. The use of Si or C as dopants further ensures compatibility with existing semiconductor manufacturing processes, facilitating integration into modern semiconductor devices.
8. The transistor structure of claim 1 , wherein: one or more of the source region and drain region further comprises a third III-V compound semiconductor material in contact with the tip region, and in contact with a sub-source or sub-drain region of the second III-V compound semiconductor material that is below the source or drain region; and the sub-source or sub-drain region also comprises the amphoteric dopant.
This invention relates to an advanced transistor structure incorporating III-V compound semiconductors, addressing challenges in high-performance electronic devices. The structure includes a channel region composed of a first III-V compound semiconductor material, with source and drain regions adjacent to the channel. These source and drain regions contain a second III-V compound semiconductor material, which may be doped with an amphoteric dopant to enhance electrical properties. A key feature is the inclusion of a third III-V compound semiconductor material within the source and drain regions. This material is in direct contact with a tip region of the channel and also interfaces with sub-source or sub-drain regions composed of the second III-V compound semiconductor material, positioned below the primary source or drain regions. The sub-source or sub-drain regions are also doped with the amphoteric dopant, ensuring uniform doping distribution and improved carrier mobility. This layered structure optimizes electrical conductivity and reduces resistance, making the transistor suitable for high-speed and low-power applications. The design leverages the unique properties of III-V materials to achieve superior performance in advanced semiconductor devices.
9. The transistor structure of claim 8 , wherein the sub-source or sub-drain region comprises a same concentration of the amphoteric dopant as the tip region, the amphoteric dopant augmenting a p-n junction at a heterojunction of the second and third III-V materials that is between the source and sub-source regions, or between the drain and sub-drain regions.
This invention relates to a transistor structure with improved performance through the use of amphoteric doping in III-V semiconductor materials. The problem addressed is the efficiency and control of current flow in transistors, particularly those using heterojunctions between different III-V materials. The structure includes a channel region composed of a first III-V material, with source and drain regions formed from second and third III-V materials. Sub-source and sub-drain regions are positioned between the channel and the source/drain regions, respectively. These sub-regions contain an amphoteric dopant at the same concentration as a tip region, which enhances the p-n junction at the heterojunction between the second and third III-V materials. This augmentation improves the electrical characteristics of the junction, facilitating better current modulation and reducing leakage. The amphoteric dopant allows the dopant to act as either a donor or acceptor depending on the surrounding material, optimizing the junction properties. The overall structure enables more efficient transistor operation by improving the interface between different semiconductor materials, addressing challenges in high-performance III-V transistors.
10. A CMOS integrated circuit (IC), comprising: a silicon substrate; an n-type III-V-channeled fin field effect transistor (FET) structure over a first region of the substrate, the n-type III-V-channeled FET structure further including: a III-V heterostructure fin including a fin of a first n-type III-V compound semiconductor material in contact with a sub-fin of a p-type III-V compound semiconductor material; a gate stack disposed over a channel region of the fin, wherein the gate stack comprises a gate electrode separated from the channel region by a gate dielectric; a source region and a drain region comprising a second n-type III-V compound semiconductor material electrically coupled to opposite ends of the channel region through a tip region of the fin, the tip region comprising an amphoteric dopant, and the tip region in contact with a sub-tip region of the sub-fin that also comprises the amphoteric dopant, wherein the amphoteric dopant activates as a donor within the first n-type III-V compound semiconductor material, and as an acceptor within the p-type III-V compound semiconductor material; and a p-type silicon-channeled FET over a second region of the substrate.
This invention relates to a CMOS integrated circuit (IC) combining silicon and III-V compound semiconductor materials to enhance performance. The IC addresses the challenge of integrating high-mobility III-V materials with conventional silicon CMOS technology, which is critical for advanced logic and RF applications. The IC includes an n-type III-V-channeled fin field-effect transistor (FET) and a p-type silicon-channeled FET on a shared silicon substrate. The n-type III-V FET features a heterostructure fin with an n-type III-V compound semiconductor material atop a p-type III-V sub-fin. A gate stack, including a gate electrode and dielectric, is disposed over the fin's channel region. The source and drain regions, made of a second n-type III-V material, connect to the channel via a tip region doped with an amphoteric dopant. This dopant acts as a donor in the n-type III-V material and as an acceptor in the p-type III-V material, ensuring efficient charge carrier modulation. The p-type silicon FET is fabricated in a separate region of the substrate, completing the CMOS architecture. This design leverages the high electron mobility of III-V materials for n-type devices while maintaining compatibility with silicon-based p-type FETs, enabling high-performance, scalable CMOS integration.
11. The CMOS IC of claim 10 , wherein: the amphoteric dopant comprises at least one of Si, C, Ge, Sn, Te, Se, and O; and the tip region and sub-tip region comprise a same concentration of the amphoteric dopant.
This invention relates to complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) with improved performance through the use of amphoteric dopants in specific regions. The technology addresses challenges in semiconductor doping, where traditional dopants (e.g., boron, phosphorus) can cause performance degradation due to diffusion, activation issues, or strain effects. Amphoteric dopants, which can act as either n-type or p-type depending on their environment, offer a solution by providing more stable and controllable doping profiles. The CMOS IC includes a transistor with a tip region and a sub-tip region, both containing an amphoteric dopant. The amphoteric dopant is selected from silicon (Si), carbon (C), germanium (Ge), tin (Sn), tellurium (Te), selenium (Se), or oxygen (O). These dopants are incorporated into the tip and sub-tip regions at the same concentration, ensuring uniform electrical properties and reducing defects. The amphoteric nature allows the dopant to adapt to the surrounding semiconductor material, minimizing strain and improving carrier mobility. This design enhances transistor performance, particularly in advanced nodes where traditional doping methods face limitations. The invention is applicable to high-performance logic devices, memory cells, and other semiconductor components requiring precise doping control.
12. The CMOS IC of claim 10 , wherein the second n-type III-V compound semiconductor material is in contact with a sub-source region or sub-drain region of the p-type III-V compound semiconductor material; and the sub-source region or sub-drain region also comprises a same concentration of the amphoteric dopant as the tip region.
This invention relates to complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) incorporating III-V compound semiconductors to enhance performance. The technology addresses challenges in conventional CMOS devices, such as limited electron mobility and poor compatibility with high-speed applications, by integrating n-type and p-type III-V materials to improve carrier mobility and device efficiency. The CMOS IC includes a p-type III-V compound semiconductor material with a tip region doped with an amphoteric dopant, which can act as either an n-type or p-type dopant depending on the semiconductor material. A second n-type III-V compound semiconductor material is in direct contact with a sub-source or sub-drain region of the p-type III-V material. The sub-source or sub-drain region also contains the same concentration of the amphoteric dopant as the tip region, ensuring uniform doping and optimized electrical properties. This configuration enhances charge carrier transport, reduces parasitic resistance, and improves overall device performance. The integration of III-V materials with controlled doping profiles enables high-speed, low-power CMOS circuits suitable for advanced electronic applications.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 27, 2015
January 28, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.