Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A transistor structure, comprising: a III-V heterostructure comprising a first III-V compound semiconductor material in contact with a second III-V compound semiconductor material; a gate stack over a channel region of the first III-V compound semiconductor material, wherein the gate stack comprises a gate electrode separated from the channel region by a gate dielectric; and a source region and a drain region electrically coupled to opposite ends of the channel region through a tip region in the first III-V compound semiconductor material, the tip region in contact with a sub-tip region of the second III-V compound semiconductor material, wherein both the tip region and sub-tip region comprise an amphoteric dopant, which activates as a donor within the first III-V compound semiconductor material, and as an acceptor within the second III-V compound semiconductor material.
2. The transistor structure of claim 1 , wherein: a majority charge carrier in the channel region is an electron; and the second III-V compound semiconductor material has p-type conductivity.
3. The transistor structure of claim 1 , wherein a sub-tip region of the second III-V compound semiconductor material comprises a same concentration of the amphoteric dopant as the tip region, the amphoteric dopant augmenting a p-n junction at the heterojunction of the first and second III-V compound semiconductor materials.
4. The transistor structure of claim 1 , wherein the first III-V material is an alloy comprising any of InGaAs, InAs, GaAs, InP, or InSb.
5. The transistor structure of claim 4 , wherein the second III-V material is an alloy comprising any of AlSb, InP, GaSb, GaAlSb, GaAsSb, InAlAs, GaAs, or AlGaAs.
6. The transistor structure of claim 1 , wherein the amphoteric dopant comprises one or more of Si, C, Ge, Sn, Te, Se, or O.
7. The transistor structure of claim 1 , wherein: the first III-V material comprises an alloy of two or more of: In, Ga, or As; and the amphoteric dopant comprises Si or C.
8. The transistor structure of claim 1 , wherein: one or more of the source region and drain region further comprises a third III-V compound semiconductor material in contact with the tip region, and in contact with a sub-source or sub-drain region of the second III-V compound semiconductor material that is below the source or drain region; and the sub-source or sub-drain region also comprises the amphoteric dopant.
9. The transistor structure of claim 8 , wherein the sub-source or sub-drain region comprises a same concentration of the amphoteric dopant as the tip region, the amphoteric dopant augmenting a p-n junction at a heterojunction of the second and third III-V materials that is between the source and sub-source regions, or between the drain and sub-drain regions.
10. A CMOS integrated circuit (IC), comprising: a silicon substrate; an n-type III-V-channeled fin field effect transistor (FET) structure over a first region of the substrate, the n-type III-V-channeled FET structure further including: a III-V heterostructure fin including a fin of a first n-type III-V compound semiconductor material in contact with a sub-fin of a p-type III-V compound semiconductor material; a gate stack disposed over a channel region of the fin, wherein the gate stack comprises a gate electrode separated from the channel region by a gate dielectric; a source region and a drain region comprising a second n-type III-V compound semiconductor material electrically coupled to opposite ends of the channel region through a tip region of the fin, the tip region comprising an amphoteric dopant, and the tip region in contact with a sub-tip region of the sub-fin that also comprises the amphoteric dopant, wherein the amphoteric dopant activates as a donor within the first n-type III-V compound semiconductor material, and as an acceptor within the p-type III-V compound semiconductor material; and a p-type silicon-channeled FET over a second region of the substrate.
11. The CMOS IC of claim 10 , wherein: the amphoteric dopant comprises at least one of Si, C, Ge, Sn, Te, Se, and O; and the tip region and sub-tip region comprise a same concentration of the amphoteric dopant.
12. The CMOS IC of claim 10 , wherein the second n-type III-V compound semiconductor material is in contact with a sub-source region or sub-drain region of the p-type III-V compound semiconductor material; and the sub-source region or sub-drain region also comprises a same concentration of the amphoteric dopant as the tip region.
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June 27, 2015
January 28, 2020
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