A semiconductor device which includes a substrate, a semiconductor chip which is mounted on the substrate, a package in which an upper surface of the substrate and the semiconductor chip are sealed using an insulating material, and a molding material which is exposed to the upper surface of the package. In addition, the device includes a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package.
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1. A semiconductor device comprising: a substrate; a semiconductor chip which is mounted on the substrate; a package which is configured by sealing an upper surface of the substrate and the semiconductor chip, using an insulating material; a mold material which is exposed to the upper surface of the package; a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package; and a pad which is formed on an upper surface of the substrate, and to which the other end of the lead is directly and electrically connected.
A semiconductor device includes a substrate and a semiconductor chip mounted on the substrate. An insulating material seals the top of the substrate and the chip, forming a package. Mold material is exposed on the top surface of the package. A lead made of a single, continuous material connects the mold material to the substrate. One end of the lead is embedded within the mold material, while the other end connects to a pad directly on the substrate's surface, establishing an electrical connection. The lead's connection point to the mold material is also exposed on the package's top surface.
2. A semiconductor device comprising: a substrate; a first semiconductor chip which is mounted on the substrate; a first package which is configured by sealing an upper surface of the substrate and the first semiconductor chip using an insulating material; a mold material which is exposed to the upper surface of the first package; a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the first package; a pad which is formed on the upper surface of the substrate, and to which the other end of the lead is directly and electrically connected; a second semiconductor chip; and a second package which is configured by sealing the second semiconductor chip, using an insulating material, and which is electrically connected to a connection portion with the mold material of the lead which is exposed to the surface of the first package.
A semiconductor device features a substrate with a first semiconductor chip mounted on it. A first package is formed by sealing the top of the substrate and the first chip using an insulating material. Mold material is exposed on the top of the first package. A lead, made of a single, continuous material, connects the mold material to the substrate, with one end embedded in the mold material and the other electrically connected to a pad directly on the substrate's surface. The lead's connection point on the mold material is exposed. A second semiconductor chip is present, along with a second package encapsulating it. The second package is electrically connected to the exposed connection point on the mold material of the lead on the first package, enabling communication between the chips.
3. The semiconductor device according to claim 2 , further comprising: solder balls which are formed on the lower surface of the second package, and are electrically connected onto the connection portion with the mold material of the lead which is exposed to the upper surface of the first package.
The semiconductor device, as described with a substrate, a first and second chip each contained within their own respective packages, and a lead connecting the mold material on the first package to a pad on the substrate, further includes solder balls. These solder balls are attached to the bottom of the second package and create an electrical connection to the exposed connection point on the mold material of the lead on the first package. This allows for simplified stacking and electrical connection of the second package to the first package through the solder ball interface.
4. A semiconductor device manufacturing method comprising: mounting a semiconductor chip onto a substrate; directly and electrically connecting the other end portion of a lead of which one end is connected to a mold material, and is integrally formed of the same material, from a connection portion with the mold material to the other end, to a pad formed on and electrically connected to the upper surface of the substrate; and forming a package by sealing an upper surface of the substrate, a semiconductor chip, the lead, and the mold material, using an insulating material, so as to expose the connection portion with the mold material of the lead and the mold material, to the upper surface of the package.
A method for manufacturing a semiconductor device involves mounting a semiconductor chip onto a substrate. A lead, made from a single, continuous material, is connected directly to a pad on the substrate. One end of the lead is connected to mold material, and the connection point on the mold material is exposed. The other end of the lead is directly and electrically connected to a pad formed on the substrate's surface. A package is then formed by sealing the top of the substrate, the semiconductor chip, the lead, and the mold material with an insulating material. This process exposes both the connection point with the mold material of the lead and the mold material itself on the top surface of the finished package.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 17, 2011
August 13, 2013
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