A semiconductor device which includes a substrate, a semiconductor chip which is mounted on the substrate, a package in which an upper surface of the substrate and the semiconductor chip are sealed using an insulating material, and a molding material which is exposed to the upper surface of the package. In addition, the device includes a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a substrate; a semiconductor chip which is mounted on the substrate; a package which is configured by sealing an upper surface of the substrate and the semiconductor chip, using an insulating material; a mold material which is exposed to the upper surface of the package; a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package; and a pad which is formed on an upper surface of the substrate, and to which the other end of the lead is directly and electrically connected.
2. A semiconductor device comprising: a substrate; a first semiconductor chip which is mounted on the substrate; a first package which is configured by sealing an upper surface of the substrate and the first semiconductor chip using an insulating material; a mold material which is exposed to the upper surface of the first package; a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the first package; a pad which is formed on the upper surface of the substrate, and to which the other end of the lead is directly and electrically connected; a second semiconductor chip; and a second package which is configured by sealing the second semiconductor chip, using an insulating material, and which is electrically connected to a connection portion with the mold material of the lead which is exposed to the surface of the first package.
3. The semiconductor device according to claim 2 , further comprising: solder balls which are formed on the lower surface of the second package, and are electrically connected onto the connection portion with the mold material of the lead which is exposed to the upper surface of the first package.
4. A semiconductor device manufacturing method comprising: mounting a semiconductor chip onto a substrate; directly and electrically connecting the other end portion of a lead of which one end is connected to a mold material, and is integrally formed of the same material, from a connection portion with the mold material to the other end, to a pad formed on and electrically connected to the upper surface of the substrate; and forming a package by sealing an upper surface of the substrate, a semiconductor chip, the lead, and the mold material, using an insulating material, so as to expose the connection portion with the mold material of the lead and the mold material, to the upper surface of the package.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 17, 2011
August 13, 2013
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