Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
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1. A method of forming an asymmetric high electron mobility transistor (HEMT), the method comprising: depositing a sacrificial material over a substrate comprising a group III-N channel layer; etching at least one trench to form a mandrel of the sacrificial material spaced apart by a first length and a second length, different from the first, from peripheral regions of the sacrificial material; conformally depositing a dielectric liner into the at least one trench and over the mandrel; depositing a bulk dielectric over the dielectric liner to fill the at least one trench; etching through the bulk dielectric and dielectric liner to expose the peripheral regions of the sacrificial material; etching the peripheral regions of the sacrificial material selectively to the dielectric liner to expose a semiconductor channel layer disposed at the periphery of the at least one trench; forming semiconductor source and drain regions in contact with the exposed semiconductor channel layer; etching through the bulk dielectric and dielectric liner to expose the mandrel; and replacing the mandrel with a gate stack.
A method for making an asymmetric GaN High Electron Mobility Transistor (HEMT) involves these steps: First, a sacrificial material is deposited on a substrate that includes a group III-Nitride channel layer. Trenches are etched to form a sacrificial material mandrel, creating different spacing lengths on either side. A dielectric liner is then deposited conformally into the trenches and over the mandrel. Next, a bulk dielectric is deposited over the liner, filling the trenches. The bulk dielectric and liner are etched to expose the sacrificial material's peripheral regions. The peripheral regions of the sacrificial material are selectively etched to expose the semiconductor channel layer at the trench periphery. Semiconductor source and drain regions are formed, contacting the exposed channel layer. Finally, the remaining bulk dielectric and liner over the mandrel are etched to expose the mandrel, which is replaced with a gate stack.
2. The method of claim 1 , wherein depositing the sacrificial material further comprises depositing a dielectric, wherein conformally depositing the dielectric liner further comprises depositing a material including a metal oxide, and wherein depositing the bulk dielectric further comprises depositing a dielectric with a lower dielectric constant than that of the dielectric liner.
This method builds upon the HEMT fabrication process described previously. The "sacrificial material" is a dielectric. The "dielectric liner" includes a metal oxide material. The "bulk dielectric" has a lower dielectric constant compared to the dielectric liner material. Essentially, this describes specific material choices for the different layers used in the HEMT fabrication process, improving performance.
3. The method of claim 2 , wherein etching through the bulk dielectric and dielectric liner further comprises: masking a region encompassing the mandrel and at least a portion of the at least one trench; and anisotropically etching the bulk dielectric and dielectric liner unprotected by the masking.
Building on the HEMT fabrication method, where a sacrificial material is deposited on a substrate, trenches are etched to form a sacrificial material mandrel, a dielectric liner conformally deposited into the trenches and over the mandrel, a bulk dielectric deposited, and then etched through the bulk dielectric and liner, this method specifies how the bulk dielectric and dielectric liner are etched. A mask is applied over the mandrel and part of the trenches. An anisotropic etch removes the unprotected bulk dielectric and dielectric liner. This allows precise removal of dielectric layers.
4. The method of claim 3 , wherein etching the peripheral regions of the sacrificial material to expose a semiconductor channel layer further comprises: isotropically etching the sacrificial material; etching a semiconductor barrier layer disposed over the channel layer; and recessing the channel layer surface with an isotropic etch to undercut an interfacial layer of the channel layer in contact with the barrier layer.
Expanding on the HEMT fabrication process, where after etching through the bulk dielectric and dielectric liner, the peripheral regions of the sacrificial material are etched to expose a semiconductor channel layer, this method details the steps for this etching process: An isotropic etch removes the sacrificial material. Any semiconductor barrier layer on top of the channel layer is etched. The channel layer surface is recessed with an isotropic etch to undercut the interfacial layer in contact with the barrier layer. This creates a clean interface between the channel and source/drain regions.
5. The method of claim 1 , wherein forming the semiconductor source and drain regions further comprises conformally growing a heavily n-type doped III-N material with a metalorganic precursor.
Concerning the formation of semiconductor source and drain regions in the HEMT fabrication process, this step involves conformally growing a heavily n-type doped group III-Nitride (III-N) material using a metalorganic precursor. This creates highly conductive source and drain contacts.
6. The method of claim 5 , wherein the heavily doped III-N material comprises InGaN doped to at least 1e19 cm −3 .
In the HEMT fabrication process where the semiconductor source and drain regions are formed by growing a heavily n-type doped III-N material using a metalorganic precursor, the heavily doped III-N material is specifically InGaN (Indium Gallium Nitride) doped to a concentration of at least 1e19 cm-3. This ensures high conductivity for the source and drain contacts.
7. The method of claim 1 , wherein etching through the bulk dielectric and dielectric liner to expose the mandrel further comprises anisotropically etching a portion of the bulk dielectric and dielectric liner disposed over the mandrel; and wherein replacing the mandrel with a gate stack further comprises: etching the sacrificial material selectively to the dielectric liner to expose and underlying semiconductor layer; conformally depositing a gate dielectric layer over the channel layer and over the dielectric liner; and depositing a gate metal over the gate dielectric layer.
In the HEMT fabrication process where the bulk dielectric and liner are etched to expose the mandrel, an anisotropic etch removes the dielectric layers over the mandrel. Subsequently, the mandrel is replaced with a gate stack, including etching the sacrificial material to expose an underlying semiconductor layer, conformally depositing a gate dielectric over the channel layer and the dielectric liner, and depositing a gate metal on top of the gate dielectric.
8. The method of claim 1 , further comprising doping a semiconductor barrier layer disposed over the channel layer with fluorine by implantation or exposure to a plasma of a fluorinated source gas.
In the HEMT fabrication process, a semiconductor barrier layer, which sits on the channel layer, is doped with fluorine. This doping is achieved either through ion implantation or by exposing the barrier layer to a fluorinated gas plasma. The fluorine doping modifies the electrical characteristics of the barrier layer.
9. The method of claim 8 , wherein replacing the mandrel with a gate stack further comprises: etching the sacrificial material selectively to the dielectric liner to expose the semiconductor barrier layer; conformally depositing a base gate dielectric layer directly on the fluorine doped semiconductor barrier layer; conformally depositing a top gate dielectric layer directly on the base gate dielectric layer; and depositing a gate metal over the top gate dielectric layer.
Building on the HEMT fabrication process which includes fluorine doping a semiconductor barrier layer, the method explains replacing the sacrificial mandrel with a gate stack. The sacrificial material is selectively etched to expose the semiconductor barrier layer. A base gate dielectric is deposited directly onto the fluorine-doped semiconductor barrier layer. Then, a top gate dielectric layer is deposited directly on the base gate dielectric layer. Finally, a gate metal is deposited over the top gate dielectric layer.
10. A method of forming a high electron mobility transistor (HEMT), the method comprising: forming a source region and a drain region in contact with a III-N semiconductor channel region disposed over a substrate; fluorine doping a semiconductor barrier layer disposed on the channel region; depositing a gate dielectric over the barrier layer, wherein depositing the gate dielectric comprises: conformally depositing a base gate dielectric layer onto the barrier layer at a first temperature; and conformally depositing a top gate dielectric layer onto the base gate dielectric layer at a second temperature, higher than the first; and depositing a gate electrode over the gate dielectric.
A method for making a High Electron Mobility Transistor (HEMT) involves forming a source and drain region in contact with a group III-Nitride semiconductor channel region on a substrate. The semiconductor barrier layer on the channel region is fluorine doped. A gate dielectric is deposited over the barrier layer by first depositing a base gate dielectric at a first temperature, then depositing a top gate dielectric onto the base dielectric at a higher second temperature. Finally, a gate electrode is deposited over the gate dielectric.
11. The method of claim 10 , wherein the fluorine doping further comprises fluorine doping at least a portion of the barrier layer to between 1e17 and 1e18 cm −3 .
Building on the HEMT fabrication process including fluorine doping of a semiconductor barrier layer, the fluorine doping is specifically controlled to achieve a concentration between 1e17 and 1e18 cm-3 within at least a portion of the barrier layer. This specified doping range optimizes transistor performance.
12. The method of claim 10 , wherein the fluorine doping further comprises: implanting or exposing the semiconductor barrier layer to a plasma of a fluorinated source gas.
This refines the fluorine doping process where a semiconductor barrier layer on the channel region is fluorine doped. The fluorine doping is achieved either through ion implantation or by exposing the semiconductor barrier layer to a plasma of a fluorinated source gas. This introduces fluorine atoms into the semiconductor lattice to alter its electrical properties.
13. The method of claim 12 , wherein the fluorine doping comprises exposing the semiconductor to a plasma of a fluorinated source gas.
Building on the HEMT fabrication process including fluorine doping of a semiconductor barrier layer, the fluorine doping specifically involves exposing the semiconductor barrier layer to a plasma of a fluorinated source gas. This method introduces fluorine into the semiconductor material.
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June 26, 2015
March 7, 2017
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