Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films.
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1. A method, comprising: forming an insulating layer on a semiconductor substrate, wherein the insulating layer comprises a trench and an open region formed in the insulating layer down to the semiconductor substrate; performing an epitaxial deposition process to deposit compound semiconductor material in the trench and in the open region of the insulating layer; terminating the epitaxial deposition process at some point in the deposition process when the trench is over filled with the compound semiconductor material, thereby forming excess compound semiconductor material protruding from the trench, and the open region is partially filled with the compound semiconductor material; depositing a layer of sacrificial material on the surface of the insulating layer to cover the excess compound semiconductor material protruding from the trench and to fill a remaining portion of the open region with the sacrificial material; and performing a CMP (chemical mechanical polishing) process to form a planarized surface by removing the sacrificial material on the surface of the insulating layer and removing the excess compound semiconductor material protruding from the trench.
A method for fabricating compound semiconductor devices involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate. Compound semiconductor material is deposited epitaxially, overfilling the trenches and partially filling the open regions. A sacrificial material is deposited to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions. Chemical mechanical polishing (CMP) is then used to create a planar surface by removing the sacrificial material and the excess semiconductor material.
2. The method of claim 1 , wherein the CMP process is performed using a chemical slurry that etches the sacrificial material and the compound semiconductor material selective to the insulating layer.
The chemical mechanical polishing (CMP) process, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using CMP to create a planar surface by removing the sacrificial material and the excess semiconductor material, uses a chemical slurry. This slurry etches both the sacrificial material and the compound semiconductor material selectively, without etching the insulating layer.
3. The method of claim 1 , wherein the compound semiconductor material comprises a III-V compound semiconductor material, wherein the III-V compound material comprises As (arsenic).
The compound semiconductor material, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, is a III-V compound semiconductor containing arsenic (As).
4. The method of claim 1 , wherein the compound semiconductor material comprises a layer of GaAs (gallium arsenide) and a layer of InGaAs (Indium Gallium Arsenide).
The compound semiconductor material, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, consists of a layer of gallium arsenide (GaAs) and a layer of indium gallium arsenide (InGaAs).
5. The method of claim 1 , wherein the sacrificial material comprises an amorphous semiconductor material.
The sacrificial material, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, is an amorphous semiconductor material.
6. The method of claim 1 , wherein the sacrificial material comprises silicon germanium (SiGe) or germanium (Ge).
The sacrificial material, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, is either silicon germanium (SiGe) or germanium (Ge).
7. The method of claim 1 , wherein the sacrificial material comprises a dielectric material.
The sacrificial material, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, is a dielectric material.
8. The method of claim 7 , wherein the dielectric material comprises silicon nitride.
The dielectric material, as described in the method for fabricating compound semiconductor devices where the sacrificial material is a dielectric material, and the method involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, is silicon nitride.
9. The method of claim 1 , wherein the compound semiconductor material in the trench comprises a fin structure of a FinFET device, and wherein the compound semiconductor material in the open region comprises one of a passive device and an isolation structure.
The compound semiconductor material in the trench, as described in the method for fabricating compound semiconductor devices that involves forming an insulating layer on a semiconductor substrate with trenches and open regions down to the substrate; depositing compound semiconductor material epitaxially, overfilling the trenches and partially filling the open regions; depositing a sacrificial material to cover the excess semiconductor material in the trenches and fill the remaining space in the open regions; and using chemical mechanical polishing (CMP) to create a planar surface by removing the sacrificial material and the excess semiconductor material, forms a fin structure of a FinFET device. The compound semiconductor material in the open region forms either a passive device or an isolation structure.
10. A semiconductor device, comprising: an insulating layer disposed on a semiconductor substrate, wherein the insulating layer comprises a trench and an open region formed in the insulating layer down to the semiconductor substrate; wherein the trench is filled with III-V compound semiconductor material that forms a fin structure of an FET (field effect transistor) device; wherein one end of the fin structure contacts the semiconductor substrate and wherein another end of the fin structure extends past a surface of the insulating layer to provide an active fin component of the FET device formed on the surface of the insulating layer; wherein a bottom portion of the open region is filled with III-V compound semiconductor material, in contact with the semiconductor substrate, wherein an upper portion of the open region is filled with as sacrificial material which comprises a non-III-V semiconductor material; and wherein the III-V compound semiconductor materials in the trench and the open region of the insulating layer are the same.
This invention relates to semiconductor devices, specifically field-effect transistors (FETs) incorporating III-V compound semiconductor materials. The device addresses challenges in integrating III-V materials with traditional silicon substrates, which is critical for enhancing performance in high-speed and low-power electronic applications. The semiconductor device includes an insulating layer on a semiconductor substrate, with a trench and an open region extending through the insulating layer to the substrate. The trench is filled with a III-V compound semiconductor material, forming a fin structure for an FET. One end of the fin structure contacts the substrate, while the other extends above the insulating layer to serve as the active fin component of the FET. The open region has a bottom portion filled with the same III-V material, ensuring continuity with the fin structure, while the upper portion is filled with a sacrificial non-III-V semiconductor material. This design enables efficient integration of III-V materials with silicon substrates, improving carrier mobility and device performance while maintaining structural stability. The use of a sacrificial material in the open region facilitates subsequent processing steps, such as selective etching or material deposition, without compromising the III-V semiconductor properties. The invention thus provides a scalable approach to incorporating III-V materials into advanced semiconductor devices.
11. The semiconductor device of claim 10 , wherein the III-V compound semiconductor material in the open region composes one of a passive device and an isolation structure.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material made of a non-III-V semiconductor, the III-V compound semiconductor material in the open region forms either a passive device or an isolation structure.
12. The semiconductor device of claim 10 , wherein the sacrificial material filling the upper portion of the open region in the insulating layer comprises an amorphous semiconductor material.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material, the sacrificial material filling the upper portion of the open region is an amorphous semiconductor material.
13. The semiconductor device of claim 10 , wherein the sacrificial material filling the upper portion of the open region in the insulating layer comprises a dielectric material.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material, the sacrificial material filling the upper portion of the open region is a dielectric material.
14. The semiconductor device of claim 13 , wherein the dielectric material comprises silicon nitride.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material which is a dielectric material, the dielectric material filling the upper portion of the open region is silicon nitride.
15. The semiconductor device of claim 10 , wherein the sacrificial material filling the upper portion of the open region in the insulating layer comprises silicon germanium (SiGe) or germanium (Ge).
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material, the sacrificial material filling the upper portion of the open region is either silicon germanium (SiGe) or germanium (Ge).
16. The semiconductor device of claim 10 , wherein the III-V compound semiconductor material that forms the fin structure comprises As (arsenic).
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material made of a non-III-V semiconductor, the III-V compound semiconductor material that forms the fin structure contains arsenic (As).
17. The semiconductor device of claim 10 , wherein the III-V compound semiconductor material that fills the trench comprises: a first layer of III-V compound semiconductor material formed on the semiconductor substrate; a second layer of III-V compound semiconductor material formed on the first layer of III-V compound semiconductor material; and a third layer of III-V compound semiconductor material formed on the second layer of III-V compound semiconductor material.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material made of a non-III-V semiconductor, the III-V compound semiconductor material that fills the trench comprises multiple layers: a first layer of III-V material on the substrate, a second layer on the first, and a third layer on the second.
18. The semiconductor device of claim 17 , wherein the first layer of III-V compound semiconductor material comprises GaAs (Gallium Arsenide), wherein the second layer of III-V compound semiconductor material comprises InP (Indium Phosphide), and wherein the third layer of III-V compound semiconductor material comprises InGaAs (Indium Gallium Arsenide).
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material made of a non-III-V semiconductor, and where the III-V compound semiconductor material that fills the trench comprises multiple layers: a first layer of III-V material on the substrate, a second layer on the first, and a third layer on the second, the first layer is gallium arsenide (GaAs), the second is indium phosphide (InP), and the third is indium gallium arsenide (InGaAs).
19. The semiconductor device of claim 17 , wherein the first layer of III-V compound semiconductor material comprises GaAs (Gallium Arsenide), wherein the second layer of III-V compound semiconductor material comprises a first composition of InGaAs (Indium Gallium Arsenide), and wherein the third layer of III-V compound semiconductor material comprises a second composition of InGaAs, which is different from the first composition of InGaAs.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material made of a non-III-V semiconductor, and where the III-V compound semiconductor material that fills the trench comprises multiple layers: a first layer of III-V material on the substrate, a second layer on the first, and a third layer on the second, the first layer is gallium arsenide (GaAs), the second layer is a first composition of indium gallium arsenide (InGaAs), and the third layer is a second, different composition of InGaAs.
20. The semiconductor device of claim 17 , wherein the first and second layers of III-V compound semiconductor material comprise a graded buffer structure that serves to match a lattice constant of material of the semiconductor substrate to a lattice constant of the third layer of III-V compound semiconductor material.
In the semiconductor device containing an insulating layer on a semiconductor substrate, a trench filled with a III-V compound semiconductor forming a FinFET fin structure with one end contacting the substrate, and an open region with its bottom portion filled with the same III-V compound semiconductor, where the upper portion of the open region is filled with a sacrificial material made of a non-III-V semiconductor, and where the III-V compound semiconductor material that fills the trench comprises multiple layers: a first layer of III-V material on the substrate, a second layer on the first, and a third layer on the second, the first and second layers form a graded buffer structure. This buffer matches the lattice constant of the semiconductor substrate to the lattice constant of the third III-V material layer.
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December 8, 2015
March 21, 2017
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