A method includes applying a first voltage to a first source line of a memory, applying a second voltage to a second source line of the memory, turning on an access transistor of a memory cell of the memory, and performing one of a write operation or a read operation on a metal-ferroelectric-semiconductor (MFS) transistor of the memory cell. Memories on which the method is performed are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory comprising: a memory cell including a pair of metal-ferroelectric-semiconductor (MFS) transistors and an access transistor; and a read-write circuit coupled to the memory cell, and configured to turn on the access transistor and to perform one of a read operation or a write operation on one of the MFS transistors in response to a command, wherein the memory cell is configured to perform a read operation on a first one of the MFS transistors when a negative voltage is applied to a gate terminal of a second one of the MFS transistors.
2. The memory of claim 1 , wherein the access transistor is one of an MFS transistor or a metaloxide-semiconductor (MOS) transistor.
3. The memory of claim 1 , further comprising a source line coupling the MFS transistors.
4. The memory of claim 1 , further comprising a local bit line coupling the MFS transistors and the access transistor.
5. The memory of claim 1 , further comprising a refresh circuit coupled to the read-write circuit and configured to generate a refresh command, wherein the read-write circuit is further configured to read data from the memory cell and to write the data read thereby back to the memory cell in response to the refresh command.
6. A method comprising: applying a first voltage to a first source line of a memory; applying a second voltage to a second source line of the memory; applying the second voltage to a gate terminal of a second metal-ferroelectric-semiconductor (MFS) transistor of a memory cell of the memory; turning on an access transistor of the memory cell of the memory; performing a write operation on a first metal-ferroelectric-semiconductor (MFS) transistor of the memory cell; and performing a read operation on a first one of the MFS transistors when a negative voltage is applied to a gate terminal of a second one of the MFS transistors.
7. The method of claim 6 , further comprising turning on an access transistor of a second memory cell of the memory.
8. The method of claim 7 , wherein the second voltage is greater than the first voltage.
9. The method of claim 8 , further comprising applying the second voltage to one of a source terminal or a drain terminal of an MFS transistor of the second memory cell.
10. The method of claim 7 , wherein the second voltage is less than the first voltage.
11. The method of claim 10 , further comprising applying the second voltage to one of a source terminal or a drain terminal of an MFS transistor of the second memory cell.
12. A method, comprising: applying a first voltage to a first source line of a memory; applying a second voltage to a second source line of the memory, wherein the first and second voltages are substantially equal; applying a negative voltage to a gate terminal of a second metal-ferroelectric-semiconductor (MFS) transistor of a memory cell of the memory; turning on an access transistor of the memory cell; and performing a read operation on a first metal-ferroelectric-semiconductor (MFS) transistor of the memory cell.
13. The method of claim 12 , further comprising turning on an access transistor of a second memory cell of the memory, and applying one of the first voltage or the second voltage to one of a source terminal or a drain terminal of an MFS transistor of the second memory cell.
14. The method of claim 12 , further comprising: applying a third voltage to the first source line of the memory; applying a fourth voltage to the second source line of the memory; turning on the access transistor of the memory cell of the memory; and performing a write operation on the first metal-ferroelectric-semiconductor (MFS) transistor of the memory cell.
15. The method of claim 14 , further comprising applying the fourth voltage to the gate terminal of the second metal-ferroelectric-semiconductor (MFS) transistor of a memory cell of the memory.
16. The method of claim 15 , further comprising turning on an access transistor of a second memory cell of the memory.
17. The method of claim 16 , wherein the second voltage is greater than the first voltage.
18. The method of claim 17 , further comprising applying the second voltage to one of a source terminal or a drain terminal of an MFS transistor of the second memory cell.
19. The method of claim 16 , wherein the second voltage is less than the first voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 27, 2016
December 26, 2017
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